![1.7Terminal Functions](/images/new-backgrounds/166612/16661227x1.webp)
Introduction
1.7Terminal Functions
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| Table 1−1. Terminal Functions | |
TERMINAL | I/O | DESCRIPTION | ||
NAME | NUMBER | |||
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Analog Video |
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VI_1_A | 80 | I/O | VI_1_A: Analog video input for CVBS/Pb/C or analog video output (see Section 2.11.59) | |
VI_1_B | 1 | I | VI_1_x: Analog video input for CVBS/Pb/C | |
VI_1_C | 2 | I | VI_2_x: Analog video input for CVBS/Y | |
VI_2_A | 7 | I | VI_3_x: Analog video input for CVBS/Pr/C | |
VI_2_B | 8 | I | VI_4_A: Analog video input for CVBS/Y | |
VI_2_C | 9 | I | Up to 10 composite, 4 | |
VI_3_A | 16 | I | can be supported. | |
VI_3_B | 17 | I | The inputs must be | |
VI_3_C | 18 | I | The possible input configurations are listed in the input select register at I2C subaddress 00h (see | |
VI_4_A | 23 | I | Section 2.11.1). | |
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Clock Signals |
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DATACLK | 40 | O | ||
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XTAL1 | 74 | I | External clock reference input. It can be connected to an external oscillator with a | |
signal or a | ||||
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XTAL2 | 75 | O | External clock reference output. Not connected if XTAL1 is driven by an external | |
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Digital Video |
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| 57, 58, |
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C_[9:0]/ | 59, 60, |
| Digital video output of CbCr, C[9] is MSB and C[0] is LSB. Also, these terminals can be programmable | |
63, 64, | I/O | |||
GPIO[9:0] | ||||
65, 66, |
| For the | ||
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| 69, 70 |
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| 43, 44, |
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| 45, 46, |
| Digital video output of Y/YCbCr, Y[9] is MSB and Y[0] is LSB. | |
Y[9:0] | 47, 50, | O | ||
For the | ||||
| 51, 52, |
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| 53, 54 |
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Miscellaneous Signals |
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GPIO | 35 | I/O | Programmable | |
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GLCO/I2CA | 37 | I/O | Genlock control output (GLCO) uses real time control (RTC) format. | |
During reset, this terminal is an input used to program the I2C address LSB. | ||||
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INTREQ | 30 | O | Interrupt request | |
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| 14, 15, |
| Not connected. These terminals can be connected to power or ground (compatible with TVP5146 | |
NC | 19, 20, |
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| terminals), internally floating. | |||
| 21, 22 |
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| Power down input: | |
PWDN | 33 | I | 1 = Power down | |
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| 0 = Normal mode | |
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RESETB | 34 | I | Reset input, active low (see Section 2.8) | |
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Host Interface |
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SCL | 28 | I | I2C clock input | |
SDA | 29 | I/O | I2C data bus |
6 | TVP5147M1PFP |