Functional Description
2.11.73 VDP Pixel Alignment Register
Subaddress | C2h−C3h |
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Default | 01Eh |
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Subaddress |
| 7 |
| 6 | 5 |
| 4 | 3 | 2 | 1 | 0 |
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C2h |
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| Pixel alignment [7:0] |
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C3h |
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| Reserved |
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| Pixel alignment [9:8] |
Pixel alignment [9:8]: These registers form a
The default value is 0x1E and has been tested with every standard supported here. A new value is needed only if a custom standard is in use.
2.11.74 VDP Line Start Register
Subaddress | D6h |
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Default | 06h |
7
6
5
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1
0
VDP line start [7:0]
VDP line start [7:0]: Set the VDP line starting address
This register must be set properly before enabling the line mode registers. The VDP processor works only the VBI region set by this register and the VDP line stop register.
2.11.75 VDP Line Stop Register
Subaddress | D7h |
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Default | 1Bh |
7
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1
0
VDP line stop [7:0]
VDP line stop [7:0]: Set the VDP stop line address
2.11.76 VDP Global Line Mode Register
Subaddress | D8h |
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Default | FFh |
7
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0
Global line mode [7:0]
Global line mode [7:0]: VDP processing for multiple lines set by the VDP start line register at subaddress D6h and the VDP stop line register at subaddress D7h.
Global line mode register has the same bit definition as the general line mode registers. General line mode has priority over the global line mode.
TVP5147M1PFP | 65 |