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TVP5147M1PFP manual Digital Audio Video, SLES140A, Data Manual, March
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TVP5147M1PFP
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Specs
Characteristics, NTSC/PAL ITU-R BT.601 Sampling
Functional Block Diagram
10. Reference Clock Configurations
Reset and I2C Bus Address Selection
NOTE Examples use default I2C address
CTI Delay Register
12. Vertical Synchronization Signals for 525-Line System
Adjusting External Syncs
Example Register Settings
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Data Manual
March 2007
Digital Audio Video
SLES140A
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Contents
SLES140A
Digital Audio Video
Data Manual
March
Products
IMPORTANT NOTICE
Applications
Introduction
Contents
July
Contents
3 Electrical Specifications
Application Information
Example Register Settings
Title
List of Illustrations
Page
Title
List of Tables
Page
1 Introduction
1.1 Detailed Functionality
1.3 Related Products
1.2 TVP5147M1 Applications
1.4 Ordering Information
Figure 1−1. Functional Block Diagram
1.5 Functional Block Diagram
1.6 Terminal Assignments
Figure 1−2. Terminal Assignments Diagram
Table 1−1. Terminal Functions
1.7 Terminal Functions
Power Supplies
Table 1−1. Terminal Functions Continued
TVP5147M1PFP
Introduction
SLES140A-March
2 Functional Description
2.1.1 Video Input Switch Control
2.1 Analog Processing and A/D Converters
Figure 2−1. Analog Processors and A/D Converters
2.1.3 Automatic Gain Control
2.1.2 Analog Input Clamping
2.1.4 Analog Video Output
2.1.5 A/D Converters
2.2 Digital Video Processing
Figure 2−2. Digital Video Processing Block Diagram
2.2.1 2⋅ Decimation Filter
2.2.2 Composite Processor
2.2.2.1 Color Low-Pass Filter
Figure 2−3. Composite and S-Video Processing Block Diagram
2.2.2.2 Y/C Separation
Characteristics, NTSC/PAL ITU-R BT.601 Sampling
Figure 2−4. Color Low-Pass Filter Frequency Response
Figure 2−5. Color Low-Pass Filter With Filter
2.2.3 Luminance Processing
Figure 2−8. Luminance Edge-Enhancer Peaking Block Diagram
2.2.4 Color Transient Improvement
Figure 2−9. Peaking Filter Response NTSC/PAL ITU-R BT.601 Sampling
2.3 Clock Circuits
Figure 2−10. Reference Clock Configurations
2.4 Real-Time Control RTC
2.5 Output Formatter
Table 2−1. Output Format
2.5.1 Separate Syncs
NOTE Line numbering conforms to ITU-R BT.470
Figure 2−12. Vertical Synchronization Signals for 525-Line System
Functional Description
Figure 2−13. Vertical Synchronization Signals for 625-Line System
NTSC
Figure 2−14. Horizontal Synchronization Signals for 10-Bit 422 Mode
NOTE ITU-R BT.656 10-bit 422 timing with 2⋅ pixel clock reference
Figure 2−15. Horizontal Synchronization Signals for 20-Bit 422 Mode
2.6 I2C Host Interface
2.5.2 Embedded Syncs
Figure 2−16. VSYNC Position With Respect to HSYNC
Table 2−3. EAV and SAV Sequence
2.6.3 VBUS Access
2.6.1 Reset and I2C Bus Address Selection
2.6.2 I2C Operation
Table 2−4. I 2C Host Interface Terminal Description
NOTE Examples use default I2C address
Figure 2−17. VBUS Access
ACK = Acknowledge generated by the slave
NAK = No acknowledge generated by the master
Table 2−6. Supported VBI System
2.7 VBI Data Processor
Table 2−7. Ancillary Data Format and Sequence
2.7.1 VBI FIFO and Ancillary Data in Video Stream
Table 2−9. Reset Sequence
2.8 Reset and Initialization
Figure 2−18. Reset Timing
2.7.2 VBI Raw Data Output
2.10 Internal Control Registers
2.9 Adjusting External Syncs
Table 2−10. I 2C Register Summary
Table 2−10. I 2C Register Summary Continued
7Ah−7Eh
Table 2−10. I 2C Register Summary Continued
84h−96h
98h−99h
Table 2−10. I 2C Register Summary Continued
Table 2−11. VBUS Register Summary
E3h−E7h
2.11.1 Input Select Register
2.11 Register Definitions
Table 2−12. Analog Channel and Video Mode Selection
2.11.3 Video Standard Register
2.11.2 AFE Gain Control Register
CVBS and S-Video
Component Video
2.11.4 Operation Mode Register
2.11.5 Autoswitch Mask Register
2.11.7 Luminance Processing Control 1 Register
2.11.6 Color Killer Register
2.11.9 Luminance Processing Control 3 Register
2.11.8 Luminance Processing Control 2 Register
Luminance Brightness Register
2.11.10
2.11.12 Chrominance Saturation Register
2.11.11 Luminance Contrast Register
2.11.13 Chroma Hue Register
2.11.14 Chrominance Processing Control 1 Register
2.11.16 AVID Start Pixel Register
2.11.15 Chrominance Processing Control 2 Register
2.11.18 HSYNC Start Pixel Register
2.11.17 AVID Stop Pixel Register
2.11.19 HSYNC Stop Pixel Register
2.11.20 VSYNC Start Line Register
2.11.21 VSYNC Stop Line Register
CTI Delay Register
2.11.22 VBLK Start Line Register
2.11.23 VBLK Stop Line Register
Sync Control Register
CTI Control Register
2.11.25
2.11.26
2.11.28 Output Formatter 2 Register
2.11.27 Output Formatter 1 Register
2.11.29 Output Formatter 3 Register
2.11.30 Output Formatter 4 Register
2.11.31 Output Formatter 5 Register
2.11.33 Clear Lost Lock Detect Register
2.11.32 Output Formatter 6 Register
2.11.34 Status 1 Register
2.11.36 AGC Gain Status Register
2.11.35 Status 2 Register
Signal present
Weak signal detection
2.11.38 GPIO Input 1 Register
2.11.37 Video Standard Status Register
Autoswitch
Video standard
AVID
2.11.39 GPIO Input 2 Register
2.11.41 AFE Coarse Gain for CH 2 Register
2.11.40 AFE Coarse Gain for CH 1 Register
2.11.43 AFE Coarse Gain for CH 4 Register
2.11.42 AFE Coarse Gain for CH 3 Register
2.11.45 AFE Fine Gain for YChroma Register
2.11.44 AFE Fine Gain for Pb Register
2.11.46 AFE Fine Gain for Pr Register
2.11.48 Field ID Control Register
2.11.47 AFE Fine Gain for CVBSLuma Register
656 version
2.11.49 F-bit and V-bit Control 1 Register
2.11.51 AGC Decrement Speed Control Register
2.11.50 Back-End AGC Control Register
2.11.52 ROM Version Register
2.11.53 AGC White Peak Processing Register
F and
2.11.54 F and V Bit Control Register
Lines per frame
F bit
2.11.55 VCR Trick Mode Control Register
2.11.58 AGC Increment Delay Register
2.11.56 Horizontal Shake Increment Register
2.11.57 AGC Increment Speed Register
2.11.60 Chip ID MSB Register
2.11.59 Analog Output Control 1 Register
2.11.61 Chip ID LSB Register
2.11.62 CPLL Speed Control Register
Status Request Register
2.11.65 AGC Decrement Delay Register
2.11.64 Vertical Line Count Register
2.11.63
2.11.66 VDP TTX Filter And Mask Registers
2.11.67 VDP TTX Filter Control Register
Figure 2−19. Teletext Filter Function
2.11.68 VDP FIFO Word Count Register
2.11.69 VDP FIFO Interrupt Threshold Register
2.11.70 VDP FIFO Reset Register
2.11.71 VDP FIFO Output Control Register
2.11.72 VDP Line Number Interrupt Register
2.11.74 VDP Line Start Register
2.11.73 VDP Pixel Alignment Register
2.11.75 VDP Line Stop Register
2.11.76 VDP Global Line Mode Register
2.11.79 VBUS Data Access With No VBUS Address Increment Register
2.11.77 VDP Full Field Enable Register
2.11.80 VBUS Data Access With VBUS Address Increment Register
2.11.78 VDP Full Field Mode Register
2.11.81 FIFO Read Data Register
2.11.82 VBUS Address Access Register
2.11.83 Interrupt Raw Status 0 Register
FIFO THRS
2.11.85 Interrupt Status 0 Register
2.11.84 Interrupt Raw Status 1 Register
Macrovision status changed
Standard changed
2.11.86 Interrupt Status 1 Register
2.11.87 Interrupt Mask 0 Register
2.11.89 Interrupt Clear 0 Register
2.11.88 Interrupt Mask 1 Register
2.11.90 Interrupt Clear 1 Register
2.12.1 VDP Closed Caption Data Register
2.12 VBUS Register Definitions
2.12.2 VDP WSS Data Register
2.12.4 VDP V-Chip TV Rating Block 1 Register
2.12.3 VDP VITC Data Register
2.12.5 VDP V-Chip TV Rating Block 2 Register
80 0530h
2.12.7 VDP V-CHIP MPAA Rating Data Register
2.12.6 VDP V-Chip TV Rating Block 3 Register
TV-G
TV-Y7
2.12.8 VDP General Line Mode and Line Address Register
VPS Read only
2.12.9 VDP VPS/Gemstar Data Register
Gemstar Read only
2.12.10 Analog Output Control 2 Register
Interrupt Configuration Register
2.12.11
3.2.1 Crystal Specifications
Electrical Specifications
3.1 Absolute Maximum Ratings†
3.2 Recommended Operating Conditions
3.3.1 DC Electrical Characteristics see Note
3.3 Electrical Characteristics
3.3.2 Analog Processing and A/D Converters
3.3.2.1 Fs = 30 MSPS for CH1, CH2
3.3.3.1 Clocks, Video Data, Sync Timing
3.3.3 Timing
3.3.3.2 I2C Host Port Timing
Figure 3−1. Clocks, Video Data, and Sync Timing
TVP5147M1PFP
Electrical Specifications
SLES140A-March
4.1.2 Recommended Settings
4 Example Register Settings
4.2.2 Recommended Settings
4.1 Example
4.3.1
4.3.2 Recommended Settings
Example
Assumptions
I2C register address 00h
TVP5147M1PFP
Example Register Settings
SLES140A-March
5.1 Application Example
5 Application Information
Figure 5−1. Example Application Circuit
5.2 Designing With PowerPADt Devices
PACKAGING INFORMATION
PACKAGE OPTION ADDENDUM
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