Example Register Settings
I2C register address 00h | = Input select register |
I2C data 46h | = Sets luma to VI_2_C and chroma to VI_1_C |
I2C register address 04h | = Autoswitch mask register |
I2C data 3Fh | = Includes NTSC 443 and PAL (M, Nc, 60) in the autoswitch |
I2C register address 08h | = Luminance processing control 3 register |
I2C data 00h | = Optimizes the trap filter selection for NTSC and PAL |
I2C register address 0Eh | = Chrominance processing control 2 register |
I2C data 04h | = Optimizes the chrominance filter selection for NTSC and PAL |
I2C register address 33h | = Output formatter 1 register |
I2C data 41h | = Selects the |
I2C register address 34h | = Output formatter 2 register |
I2C data 11h | = Enables YCbCr output and the clock output |
I2C register address 36h | = Output formatter 4 register |
I2C data 11h | = Enables HS and VS sync outputs |
4.3 | Example 3 |
4.3.1 | Assumptions |
Input connector: | Component [VI_1_B (Pb), VI_2_B (Y), VI_3_B (Pr)] |
Video format: | 480I, 576I |
Output format: |
4.3.2 Recommended Settings
Recommended I2C writes: This setup requires additional writes to output the discrete sync
84 | TVP5147M1PFP |