Output Formatter 5 Register | Texas Instruments TVP5147M1PFP

Functional Description

2.11.31 Output Formatter 5 Register

Subaddress	37h

Default	FFh

7	6	5		4	3	2	1		0

C_5 [1:0]			C_4 [1:0]		C_3 [1:0]			C_2 [1:0]

C_5 [1:0]: C_5 terminal function select

00 = C_5 is logic 0 output.

01 = C_5 is logic 1 output.

10 = Reserved

11 = C_5 is logic input (default).

C_4 [1:0]: C_4 terminal function select

00 = C_4 is logic 0 output.

01 = C_4 is logic 1 output.

10 = Reserved

11 = C_4 is logic input (default).

C_3 [1:0]: C_3 terminal function select

00 = C_3 is logic 0 output.

01 = C_3 is logic 1 output.

10 = Reserved

11 = C_3 is logic input (default).

C_2 [1:0]: C_2 terminal function select

00 = C_2 is logic 0 output.

01 = C_2 is logic 1 output.

10 = Reserved

11 = C_2 is logic input (default).

C_x functions are only available in the 10-bit output mode.

TVP5147M1PFP

SLES140A—March 2007

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Texas Instruments TVP5147M1PFP manual Output Formatter 5 Register

TVP5147M1PFP specifications

The Texas Instruments TVP5147M1PFP is a versatile video decoder that stands out in the realm of analog video processing. This device is particularly designed for high-quality video applications, making it an excellent choice for a variety of consumer and professional electronics that require reliable video decoding capabilities.

One of the main features of the TVP5147 is its ability to decode multiple video formats, including NTSC, PAL, and SECAM. This flexibility allows the decoder to seamlessly interface with various video sources from different geographic regions, providing a global solution for video applications. The TVP5147 includes advanced synchronization features, ensuring it can effectively handle video signals that may vary in timing and quality.

The device is equipped with a sophisticated 10-bit analog-to-digital converter (ADC), which enhances the precision and clarity of the digital video output. This high-resolution capability allows for improved color accuracy and detail, leading to a more lifelike video representation. Additionally, the TVP5147 utilizes advanced digital processing technologies, including noise reduction and image enhancement features, contributing to outstanding image quality even in less than ideal input conditions.

Another notable characteristic of the TVP5147M1PFP is its support for various output formats, including ITU-R BT.601 and 656, which facilitates easy integration into different systems. The device can also provide various output resolutions, catering to the needs of diverse applications ranging from standard definition to high definition displays.

In terms of connectivity, the TVP5147 offers multiple input options, including composite video, S-video, and component video interfaces. This versatility ensures that it can accommodate a wide range of video sources, from traditional VHS players to modern digital cameras. Furthermore, the integrated video control features allow for easy adjustment of parameters such as brightness, contrast, and saturation.

The power consumption of the TVP5147M1PFP is optimized for low-energy applications while maintaining high performance, making it suitable for battery-powered devices and energy-efficient designs. Overall, the Texas Instruments TVP5147M1PFP is an exceptional video decoder that blends flexibility, high quality, and advanced technology, making it a preferred choice for video processing in numerous consumer and industrial applications. Its combination of features ensures reliable performance and high-quality output, fulfilling the demands of modern multimedia environments.

Contents

Data Manual Important Notice Contents Section 11.11 Section 11.59 Example List of Illustrations List of Tables Introduction Detailed Functionality TVP5147M1 Applications Related ProductsOrdering Information Packaged Devices Functional Block Diagram Terminal Assignments PFP Package TOP View Miscellaneous Signals Terminal Functions−1. Terminal Functions Terminal Description Name Number Sync Signals VS/VBLK/GPIO Introduction Video Input Switch Control Analog Processing and A/D ConvertersPGA ADC Analog Input Clamping Automatic Gain ControlAnalog Video Output 5 A/D Converters 1 2⋅ Decimation Filter Digital Video ProcessingComposite Processor NTSC/PAL CVBS/C −10 − dB −20 −30 −40−50 −60 −70 −10 Color Transient Improvement Luminance ProcessingOUT Real-Time Control RTC Clock CircuitsOutput Formatter Separate Syncs −1. Output FormatTerminal Name Number FID Vblk Line 525 First Field Video VS StartVblk Start 622 623 624 625 First Field Video VS Start Vblk Start 23 24 Vblk Stop 336 337 Horizontal Blanking Cb0 Cr0 HS Start HS Stop Avid Stop Dataclk = 2⋅ Pixel Clock ModeAvid Start −15. Horizontal Synchronization Signals for 20-Bit 422 Mode Avid Stop Dataclk = 1⋅ Pixel Clock Mode Embedded Syncs I2C Host Interface−3. EAV and SAV Sequence D9 MSB Reset and I2C Bus Address Selection Vbus Access2 I2C Operation −4. I 2C Host Interface Terminal Description Host I2CVbus WSS Vitc −6. Supported VBI System VBI Data ProcessorVBI System Standard Line Number Number of Bytes VBI Fifo and Ancillary Data in Video Stream −7. Ancillary Data Format and SequenceByte Description LSB Reset and Initialization −9. Reset SequenceVBI Raw Data Output −8. VBI Raw Data Output Format Adjusting External Syncs Register Name 2C Subaddress DefaultInternal Control Registers −10. I 2C Register Summary Vblk start line V bit control 75h 12h VCR trick mode control 76h −11. Vbus Register Summary −12. Analog Channel and Video Mode Selection Mode Inputs Selected Input Select Output HEXRegister Definitions Input Select Register Video Standard Register AFE Gain Control RegisterCvbs and S-Video Component Video Autoswitch Mask Register Operation Mode RegisterSubaddress 03h Default 00h Color Killer Register Luminance Processing Control 1 Register Subaddress 08h Default 02h Reserved Trap filter select Luminance Processing Control 2 RegisterLuminance Processing Control 3 Register Luminance Brightness Register Luminance Contrast Register Chrominance Saturation RegisterChroma Hue Register Chrominance Processing Control 1 Register Subaddress 0Eh Default Chrominance Processing Control 2 RegisterAvid Start Pixel Register WCF Avid Stop Pixel Register Hsync Start Pixel RegisterHsync Stop Pixel Register Vsync Start Line Register CTI Delay Register Vsync Stop Line RegisterVblk Start Line Register Vblk Stop Line Register CTI Control Register Subaddress 2Eh Default 00h CTI coring CTI gainSync Control Register Subaddress 33h Default 40h Output Formatter 1 RegisterOutput Formatter 2 Register CbCr code Reserved Output Formatter 3 Register Output Formatter 4 Register Output Formatter 5 Register Output Formatter 6 Register Subaddress 39h Default 00hClear Lost Lock Detect Register Status 1 Register Read only Status 2 Register AGC Gain Status RegisterColor killed Subaddress 3Ch Fine gain 3Dh Coarse gain Video Standard Status Register Gpio Input 1 Register Gpio Input 2 Register Glco FID Subaddress 46h Default 20h Cgain 1 Reserved Subaddress 47h Default 20h Cgain 2 ReservedAFE Coarse Gain for CH 1 Register AFE Coarse Gain for CH 2 Register Subaddress 48h Default 20h Cgain 3 Reserved Subaddress 49h Default 20h Cgain 4 ReservedAFE Coarse Gain for CH 3 Register AFE Coarse Gain for CH 4 Register AFE Fine Gain for YChroma Register AFE Fine Gain for Pb RegisterAFE Fine Gain for Pr Register Subaddress 57h Default 00h AFE Fine Gain for CVBSLuma RegisterField ID Control Register FID control Subaddress 69h Default 00h Bit modeReg 69h Reg 75h Mode Standard LPF Nonstandard LPF Bit Bit and V-bit Control 1 Register AGC Decrement Speed Control Register Back-End AGC Control RegisterROM Version Register AGC White Peak Processing Register Subaddress 74h Default 00h Luma peak aLuma peak B Composite peak V Bit Control Register Lines per frame Bit VCR Trick Mode Control Register AGC Increment Delay RegisterHorizontal Shake Increment Register AGC Increment Speed Register Analog Output Control 1 Register Chip ID MSB RegisterChip ID LSB Register Cpll Speed Control Register Status Request Register AGC Decrement Delay RegisterVertical Line Count Register VDP TTX Filter And Mask Registers VDP TTX Filter Control Register VDP Fifo Word Count Register NibbleFilter Pass VDP Fifo Reset Register VDP Fifo Interrupt Threshold RegisterVDP Fifo Output Control Register VDP Line Number Interrupt Register VDP Global Line Mode Register VDP Pixel Alignment RegisterVDP Line Start Register VDP Line Stop Register VDP Full Field Enable Register VDP Full Field Mode RegisterVbus Data Access With No Vbus Address Increment Register Vbus Data Access With Vbus Address Increment Register Vbus Address Access Register Fifo Read Data RegisterInterrupt Raw Status 0 Register Fifo Thrs TTX WSS VPS Vitc CC F2 CC F1 Interrupt Raw Status 1 Register Interrupt Status 0 RegisterReserved Lock Fifo full Interrupt Status 1 Register Interrupt Mask 0 Register Interrupt Mask 1 Register Subaddress F5h Default 00hInterrupt Clear 0 Register Subaddress F7h Default 00h Interrupt Clear 1 Register Vbus Register Definitions VDP Closed Caption Data RegisterVDP WSS Data Register Subaddress Byte VDP V-Chip TV Rating Block 1 Register VDP Vitc Data RegisterVDP V-Chip TV Rating Block 2 Register VDP V-Chip TV Rating Block 3 Register VDP V-CHIP Mpaa Rating Data RegisterNone TV-PG VDP General Line Mode and Line Address Register Default line mode = FFh, address = 00h VDP VPS/Gemstar Data Register VPS Read only Interrupt Configuration Register Analog Output Control 2 Register Crystal Specifications Crystal Specifications MIN NOM MAX UnitAbsolute Maximum Ratings† Recommended Operating Conditions Electrical Characteristics DC Electrical Characteristics see NoteAnalog Processing and A/D Converters Parameter Test Conditions MIN TYP MAX Unit Timing Dataclk AVID, VS, HS, FIDVOH VOL VC1 SDA VC0 SCL Electrical Specifications Example Recommended SettingsAssumptions Assumptions Example Register Settings Example Register Settings Application Example −1. Example Application Circuit Designing With PowerPADt Devices MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page