Application Example | Texas Instruments TVP5147M1PFP manual

Application Information

5 Application Information

5.1Application Example

22Ω

VOUT

75 Ω

1 kΩ

VI_1A

VI_1B

VI_1C

75 Ω (3)

VI_2A

VI_2B

VI_2C

75 Ω (3)

VI_3A

VI_3B

VI_3C

75 Ω (3)

FID

A3.3VDD

A1.8VDD

12kΩ

0.1∝F (2)

22 ∝F

22 kΩ

		1
		2
	0.1 ∝F (3)	3
	0.1 ∝F (3)	4
		4
	0.1 ∝F (2)	5
	0.1 ∝F (2)	6
	0.1 ∝F (3)	6
	0.1 ∝F (3)	7
		7
		8
		9
		10
		11
		12
	0.1 ∝F (3)	13
	0.1 ∝F (3)	14
		14
		15
		16
		17
		18
	0.1 ∝F (3)	19
	0.1 ∝F (3)	20
		20

0.1∝F

C0

2.2 kΩ

VS/VBLK

C1

C2

HS/CS

IOVDD3.3V

C3

XTAL1

C4

DVDD1.8V

XTAL2

C5

0.1 ∝F (2)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

VI 1 A

CH1 A18GND

CH1 A18VDD

PLL A18GND

PLL A18VDD

XTAL2

XTAL1

VS/VBLK

HS/CS

FID

C 0

C 1

DGND

DVDD

C 2

C 3

C 4

C 5

IOGND

IOVDD

VI_1_B

C_6

60

C6

59

VI_1_C

C_7

C7

58

CH1_A33GND

C_8

C8

57

CH1_A33VDD

C_9

C9

56

CH2_A33VDD

DGND

55

CH2_A33GND

DVDD

54

0.1 ∝F

VI_2_A

Y_0

Y_0

53

VI_2_B

Y_1

Y_1

52

VI_2_C

Y_2

Y_2

51

CH2_A18GND

Y_3

Y_3

TVP5147M1

50

CH2_A18VDD

Y_4

Y_4

49

A18VDD_REF

IOGND

48

A18GND_REF

IOVDD

47

NC

Y_5

Y_5

0.1 ∝F

46

NC

Y_6

Y_6

45

VI_3_A

Y_7

Y_7

44

VI_3_B

Y_8

Y_8

43

VI_3_C

Y_9

Y_9

42

NC

DGND

41

NC

DVDD

0.1 ∝F

NC

NC

VI 4A

A18GND

A18VDD

AGND

DGND

SCL

SDA

INTREQ

DVDD

DGND

PWDN

RESETB

FSS

AVID

GLCO/I2CA

IOVDD

IOGND

DATACLK

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

VI_4A

CL1

0.1∝F

75 Ω

	GND
XTAL1		IOVDD
XTAL1
XTAL2		10 kΩ
		10 kΩ
14.31818 MHz	GLCO/I2CA	2	1
		2
CL2		10 kΩ	3
CL2		10 kΩ

0.1 ∝F

I2C Address selection 1−2 Base Addr. 0xBA 2−3 Base Addr. 0xB8

0.1 ∝F

0.1 ∝F

2.2 kΩ (2)

DATACLK

GLCO/I2CA

AVID

FSS

RESETB

PWDN

INTREQ

SDA

SCL

NOTE: If XTAL1 is connected to clock source, input voltage high must be 1.8 V. TVP5147 can be a drop-in replacement for TVP5146.

Terminals 69 and 71 must be connected to ground through pulldown resistors.

Figure 5−1. Example Application Circuit

SLES140A—March 2007

TVP5147M1PFP

87

Image 95

Texas Instruments TVP5147M1PFP manual Application Example, 1. Example Application Circuit

TVP5147M1PFP specifications

The Texas Instruments TVP5147M1PFP is a versatile video decoder that stands out in the realm of analog video processing. This device is particularly designed for high-quality video applications, making it an excellent choice for a variety of consumer and professional electronics that require reliable video decoding capabilities.

One of the main features of the TVP5147 is its ability to decode multiple video formats, including NTSC, PAL, and SECAM. This flexibility allows the decoder to seamlessly interface with various video sources from different geographic regions, providing a global solution for video applications. The TVP5147 includes advanced synchronization features, ensuring it can effectively handle video signals that may vary in timing and quality.

The device is equipped with a sophisticated 10-bit analog-to-digital converter (ADC), which enhances the precision and clarity of the digital video output. This high-resolution capability allows for improved color accuracy and detail, leading to a more lifelike video representation. Additionally, the TVP5147 utilizes advanced digital processing technologies, including noise reduction and image enhancement features, contributing to outstanding image quality even in less than ideal input conditions.

Another notable characteristic of the TVP5147M1PFP is its support for various output formats, including ITU-R BT.601 and 656, which facilitates easy integration into different systems. The device can also provide various output resolutions, catering to the needs of diverse applications ranging from standard definition to high definition displays.

In terms of connectivity, the TVP5147 offers multiple input options, including composite video, S-video, and component video interfaces. This versatility ensures that it can accommodate a wide range of video sources, from traditional VHS players to modern digital cameras. Furthermore, the integrated video control features allow for easy adjustment of parameters such as brightness, contrast, and saturation.

The power consumption of the TVP5147M1PFP is optimized for low-energy applications while maintaining high performance, making it suitable for battery-powered devices and energy-efficient designs. Overall, the Texas Instruments TVP5147M1PFP is an exceptional video decoder that blends flexibility, high quality, and advanced technology, making it a preferred choice for video processing in numerous consumer and industrial applications. Its combination of features ensures reliable performance and high-quality output, fulfilling the demands of modern multimedia environments.

Contents

Data Manual Important Notice Contents Section 11.11 Section 11.59 Example List of Illustrations List of Tables Introduction Detailed Functionality Packaged Devices TVP5147M1 ApplicationsRelated Products Ordering Information Functional Block Diagram PFP Package TOP View Terminal Assignments Terminal Description Name Number Miscellaneous SignalsTerminal Functions −1. Terminal Functions VS/VBLK/GPIO Sync Signals Introduction ADC Video Input Switch ControlAnalog Processing and A/D Converters PGA 5 A/D Converters Analog Input ClampingAutomatic Gain Control Analog Video Output Composite Processor Digital Video Processing1 2⋅ Decimation Filter CVBS/C NTSC/PAL −10 −10 − dB −20−30 −40 −50 −60 −70 OUT Luminance ProcessingColor Transient Improvement Output Formatter Clock CircuitsReal-Time Control RTC Name Number Separate Syncs−1. Output Format Terminal Vblk Start Line 525 First Field Video VS StartFID Vblk Vblk Start 23 24 Vblk Stop 336 337 622 623 624 625 First Field Video VS Start Avid Start Avid Stop Dataclk = 2⋅ Pixel Clock ModeHorizontal Blanking Cb0 Cr0 HS Start HS Stop Avid Stop Dataclk = 1⋅ Pixel Clock Mode −15. Horizontal Synchronization Signals for 20-Bit 422 Mode D9 MSB Embedded SyncsI2C Host Interface −3. EAV and SAV Sequence −4. I 2C Host Interface Terminal Description Reset and I2C Bus Address SelectionVbus Access 2 I2C Operation WSS Vitc HostI2C Vbus VBI System Standard Line Number Number of Bytes VBI Data Processor−6. Supported VBI System LSB VBI Fifo and Ancillary Data in Video Stream−7. Ancillary Data Format and Sequence Byte Description −8. VBI Raw Data Output Format Reset and Initialization−9. Reset Sequence VBI Raw Data Output −10. I 2C Register Summary Adjusting External SyncsRegister Name 2C Subaddress Default Internal Control Registers Vblk start line V bit control 75h 12h VCR trick mode control 76h −11. Vbus Register Summary Input Select Register −12. Analog Channel and Video Mode SelectionMode Inputs Selected Input Select Output HEX Register Definitions Cvbs and S-Video Component Video AFE Gain Control RegisterVideo Standard Register Subaddress 03h Default 00h Operation Mode RegisterAutoswitch Mask Register Luminance Processing Control 1 Register Color Killer Register Luminance Brightness Register Subaddress 08h Default 02h Reserved Trap filter selectLuminance Processing Control 2 Register Luminance Processing Control 3 Register Chrominance Processing Control 1 Register Luminance Contrast RegisterChrominance Saturation Register Chroma Hue Register WCF Subaddress 0Eh DefaultChrominance Processing Control 2 Register Avid Start Pixel Register Vsync Start Line Register Avid Stop Pixel RegisterHsync Start Pixel Register Hsync Stop Pixel Register Vblk Stop Line Register CTI Delay RegisterVsync Stop Line Register Vblk Start Line Register Sync Control Register Subaddress 2Eh Default 00h CTI coring CTI gainCTI Control Register CbCr code Reserved Subaddress 33h Default 40hOutput Formatter 1 Register Output Formatter 2 Register Output Formatter 3 Register Output Formatter 4 Register Output Formatter 5 Register Clear Lost Lock Detect Register Subaddress 39h Default 00hOutput Formatter 6 Register Read only Status 1 Register Subaddress 3Ch Fine gain 3Dh Coarse gain Status 2 RegisterAGC Gain Status Register Color killed Gpio Input 1 Register Video Standard Status Register Glco FID Gpio Input 2 Register AFE Coarse Gain for CH 2 Register Subaddress 46h Default 20h Cgain 1 ReservedSubaddress 47h Default 20h Cgain 2 Reserved AFE Coarse Gain for CH 1 Register AFE Coarse Gain for CH 4 Register Subaddress 48h Default 20h Cgain 3 ReservedSubaddress 49h Default 20h Cgain 4 Reserved AFE Coarse Gain for CH 3 Register AFE Fine Gain for Pr Register AFE Fine Gain for Pb RegisterAFE Fine Gain for YChroma Register FID control Subaddress 57h Default 00hAFE Fine Gain for CVBSLuma Register Field ID Control Register Bit and V-bit Control 1 Register Subaddress 69h Default 00hBit mode Reg 69h Reg 75h Mode Standard LPF Nonstandard LPF Bit ROM Version Register Back-End AGC Control RegisterAGC Decrement Speed Control Register Luma peak B Composite peak Subaddress 74h Default 00h Luma peak aAGC White Peak Processing Register Lines per frame Bit V Bit Control Register AGC Increment Speed Register VCR Trick Mode Control RegisterAGC Increment Delay Register Horizontal Shake Increment Register Cpll Speed Control Register Analog Output Control 1 RegisterChip ID MSB Register Chip ID LSB Register Vertical Line Count Register AGC Decrement Delay RegisterStatus Request Register VDP TTX Filter And Mask Registers VDP TTX Filter Control Register Pass VDP Fifo Word Count RegisterNibble Filter VDP Line Number Interrupt Register VDP Fifo Reset RegisterVDP Fifo Interrupt Threshold Register VDP Fifo Output Control Register VDP Line Stop Register VDP Global Line Mode RegisterVDP Pixel Alignment Register VDP Line Start Register Vbus Data Access With Vbus Address Increment Register VDP Full Field Enable RegisterVDP Full Field Mode Register Vbus Data Access With No Vbus Address Increment Register Fifo Thrs TTX WSS VPS Vitc CC F2 CC F1 Vbus Address Access RegisterFifo Read Data Register Interrupt Raw Status 0 Register Fifo full Interrupt Raw Status 1 RegisterInterrupt Status 0 Register Reserved Lock Interrupt Status 1 Register Interrupt Mask 0 Register Interrupt Clear 0 Register Subaddress F5h Default 00hInterrupt Mask 1 Register Interrupt Clear 1 Register Subaddress F7h Default 00h Subaddress Byte Vbus Register DefinitionsVDP Closed Caption Data Register VDP WSS Data Register VDP V-Chip TV Rating Block 2 Register VDP Vitc Data RegisterVDP V-Chip TV Rating Block 1 Register TV-PG VDP V-Chip TV Rating Block 3 RegisterVDP V-CHIP Mpaa Rating Data Register None Default line mode = FFh, address = 00h VDP General Line Mode and Line Address Register VPS Read only VDP VPS/Gemstar Data Register Analog Output Control 2 Register Interrupt Configuration Register Recommended Operating Conditions Crystal SpecificationsCrystal Specifications MIN NOM MAX Unit Absolute Maximum Ratings† Parameter Test Conditions MIN TYP MAX Unit Electrical CharacteristicsDC Electrical Characteristics see Note Analog Processing and A/D Converters VC1 SDA VC0 SCL TimingDataclk AVID, VS, HS, FID VOH VOL Electrical Specifications Assumptions Recommended SettingsExample Assumptions Example Register Settings Example Register Settings −1. Example Application Circuit Application Example Designing With PowerPADt Devices Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page