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Texas Instruments TVP5147M1PFP manual Chrominance Processing Control 2 Register

Models: TVP5147M1PFP

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									Functional Description
2.11.15 Chrominance Processing Control 2 Register

Subaddress	0Eh

Default	0Eh

7	6		5		4	3	2	1		0

		Reserved				PAL compensation	WCF	Chrominance filter select [1:0]

PAL compensation:

0 = Disabled

1 = Enabled (default)

Wideband chroma LPF filter (WCF):

0 = Disabled

1 = Enabled (default)

Chrominance filter select [1:0]:

00 = Disabled

01 = Notch 1

10 = Notch 2 (default)

11 = Notch 3

See Figure 2−6 and Figure 2−7 for characteristics.

2.11.16 AVID Start Pixel Register

Subaddress		16h−17h

Default		055h

Subaddress		7		6	5	4	3		2	1	0

16h						AVID start [7:0]

17h				Reserved		AVID active		Reserved		AVID start [9:8]

AVID active:

0 = AVID out active in VBLK (default)

1 = AVID out inactive in VBLK

AVID start [9:0]: AVID start pixel number, this is an absolute pixel location from HSYNC start pixel 0.

	NTSC 601	NTSC Sqp	PAL 601	PAL Sqp
default	85 (55h)	86 (56h)	88 (58h)	103 (67h)

The TVP5147M1 decoder updates the AVID start only when the AVID start MSB byte is written to. If the user changes these registers, then the TVP5147M1 decoder retains values in different modes until this device resets. The AVID start pixel register also controls the position of the SAV code.

SLES140A—March 2007

TVP5147M1PFP

37

Image 45

Texas Instruments TVP5147M1PFP manual Chrominance Processing Control 2 Register, AVID Start Pixel Register

Contents

SLES140A Digital Audio VideoData Manual MarchIMPORTANT NOTICE ProductsApplications Introduction ContentsJuly Contents 3 Electrical SpecificationsApplication Information Example Register SettingsList of Illustrations TitlePage List of Tables TitlePage 1 Introduction 1.1 Detailed Functionality 1.2 TVP5147M1 Applications 1.3 Related Products1.4 Ordering Information Figure 1−1. Functional Block Diagram 1.5 Functional Block Diagram1.6 Terminal Assignments Figure 1−2. Terminal Assignments DiagramTable 1−1. Terminal Functions 1.7 Terminal FunctionsPower Supplies Table 1−1. Terminal Functions ContinuedIntroduction TVP5147M1PFPSLES140A-March 2 Functional Description 2.1.1 Video Input Switch Control2.1 Analog Processing and A/D Converters Figure 2−1. Analog Processors and A/D Converters2.1.3 Automatic Gain Control 2.1.2 Analog Input Clamping2.1.4 Analog Video Output 2.1.5 A/D Converters2.2 Digital Video Processing Figure 2−2. Digital Video Processing Block Diagram2.2.1 2⋅ Decimation Filter 2.2.2 Composite Processor2.2.2.1 Color Low-Pass Filter Figure 2−3. Composite and S-Video Processing Block Diagram2.2.2.2 Y/C Separation Characteristics, NTSC/PAL ITU-R BT.601 SamplingFigure 2−4. Color Low-Pass Filter Frequency Response Figure 2−5. Color Low-Pass Filter With Filter2.2.3 Luminance Processing Figure 2−8. Luminance Edge-Enhancer Peaking Block Diagram2.2.4 Color Transient Improvement Figure 2−9. Peaking Filter Response NTSC/PAL ITU-R BT.601 Sampling2.3 Clock Circuits Figure 2−10. Reference Clock Configurations2.4 Real-Time Control RTC 2.5 Output FormatterTable 2−1. Output Format 2.5.1 Separate SyncsNOTE Line numbering conforms to ITU-R BT.470 Figure 2−12. Vertical Synchronization Signals for 525-Line SystemFunctional Description Figure 2−13. Vertical Synchronization Signals for 625-Line SystemFigure 2−14. Horizontal Synchronization Signals for 10-Bit 422 Mode NTSCNOTE ITU-R BT.656 10-bit 422 timing with 2⋅ pixel clock reference Figure 2−15. Horizontal Synchronization Signals for 20-Bit 422 Mode 2.6 I2C Host Interface 2.5.2 Embedded SyncsFigure 2−16. VSYNC Position With Respect to HSYNC Table 2−3. EAV and SAV Sequence2.6.3 VBUS Access 2.6.1 Reset and I2C Bus Address Selection2.6.2 I2C Operation Table 2−4. I 2C Host Interface Terminal DescriptionNOTE Examples use default I2C address Figure 2−17. VBUS AccessACK = Acknowledge generated by the slave NAK = No acknowledge generated by the masterTable 2−6. Supported VBI System 2.7 VBI Data ProcessorTable 2−7. Ancillary Data Format and Sequence 2.7.1 VBI FIFO and Ancillary Data in Video StreamTable 2−9. Reset Sequence 2.8 Reset and InitializationFigure 2−18. Reset Timing 2.7.2 VBI Raw Data Output2.9 Adjusting External Syncs 2.10 Internal Control RegistersTable 2−10. I 2C Register Summary Table 2−10. I 2C Register Summary Continued 7Ah−7Eh Table 2−10. I 2C Register Summary Continued84h−96h 98h−99hTable 2−11. VBUS Register Summary Table 2−10. I 2C Register Summary ContinuedE3h−E7h 2.11 Register Definitions 2.11.1 Input Select RegisterTable 2−12. Analog Channel and Video Mode Selection 2.11.3 Video Standard Register 2.11.2 AFE Gain Control RegisterCVBS and S-Video Component Video2.11.4 Operation Mode Register 2.11.5 Autoswitch Mask Register2.11.7 Luminance Processing Control 1 Register 2.11.6 Color Killer Register2.11.9 Luminance Processing Control 3 Register 2.11.8 Luminance Processing Control 2 RegisterLuminance Brightness Register 2.11.102.11.12 Chrominance Saturation Register 2.11.11 Luminance Contrast Register2.11.13 Chroma Hue Register 2.11.14 Chrominance Processing Control 1 Register2.11.16 AVID Start Pixel Register 2.11.15 Chrominance Processing Control 2 Register2.11.18 HSYNC Start Pixel Register 2.11.17 AVID Stop Pixel Register2.11.19 HSYNC Stop Pixel Register 2.11.20 VSYNC Start Line Register2.11.21 VSYNC Stop Line Register CTI Delay Register2.11.22 VBLK Start Line Register 2.11.23 VBLK Stop Line RegisterSync Control Register CTI Control Register2.11.25 2.11.262.11.28 Output Formatter 2 Register 2.11.27 Output Formatter 1 Register2.11.29 Output Formatter 3 Register 2.11.30 Output Formatter 4 Register 2.11.31 Output Formatter 5 Register 2.11.33 Clear Lost Lock Detect Register 2.11.32 Output Formatter 6 Register2.11.34 Status 1 Register 2.11.36 AGC Gain Status Register 2.11.35 Status 2 RegisterSignal present Weak signal detection2.11.38 GPIO Input 1 Register 2.11.37 Video Standard Status RegisterAutoswitch Video standardAVID 2.11.39 GPIO Input 2 Register2.11.41 AFE Coarse Gain for CH 2 Register 2.11.40 AFE Coarse Gain for CH 1 Register2.11.43 AFE Coarse Gain for CH 4 Register 2.11.42 AFE Coarse Gain for CH 3 Register2.11.44 AFE Fine Gain for Pb Register 2.11.45 AFE Fine Gain for YChroma Register2.11.46 AFE Fine Gain for Pr Register 2.11.47 AFE Fine Gain for CVBSLuma Register 2.11.48 Field ID Control Register656 version 2.11.49 F-bit and V-bit Control 1 Register 2.11.50 Back-End AGC Control Register 2.11.51 AGC Decrement Speed Control Register2.11.52 ROM Version Register 2.11.53 AGC White Peak Processing Register F and 2.11.54 F and V Bit Control RegisterLines per frame F bit2.11.55 VCR Trick Mode Control Register 2.11.58 AGC Increment Delay Register2.11.56 Horizontal Shake Increment Register 2.11.57 AGC Increment Speed Register2.11.60 Chip ID MSB Register 2.11.59 Analog Output Control 1 Register2.11.61 Chip ID LSB Register 2.11.62 CPLL Speed Control RegisterStatus Request Register 2.11.65 AGC Decrement Delay Register2.11.64 Vertical Line Count Register 2.11.632.11.66 VDP TTX Filter And Mask Registers 2.11.67 VDP TTX Filter Control Register Figure 2−19. Teletext Filter Function 2.11.68 VDP FIFO Word Count Register2.11.69 VDP FIFO Interrupt Threshold Register 2.11.70 VDP FIFO Reset Register2.11.71 VDP FIFO Output Control Register 2.11.72 VDP Line Number Interrupt Register2.11.74 VDP Line Start Register 2.11.73 VDP Pixel Alignment Register2.11.75 VDP Line Stop Register 2.11.76 VDP Global Line Mode Register2.11.79 VBUS Data Access With No VBUS Address Increment Register 2.11.77 VDP Full Field Enable Register2.11.80 VBUS Data Access With VBUS Address Increment Register 2.11.78 VDP Full Field Mode Register2.11.81 FIFO Read Data Register 2.11.82 VBUS Address Access Register2.11.83 Interrupt Raw Status 0 Register FIFO THRS2.11.85 Interrupt Status 0 Register 2.11.84 Interrupt Raw Status 1 RegisterMacrovision status changed Standard changed2.11.86 Interrupt Status 1 Register 2.11.87 Interrupt Mask 0 Register 2.11.89 Interrupt Clear 0 Register 2.11.88 Interrupt Mask 1 Register2.11.90 Interrupt Clear 1 Register 2.12 VBUS Register Definitions 2.12.1 VDP Closed Caption Data Register2.12.2 VDP WSS Data Register 2.12.4 VDP V-Chip TV Rating Block 1 Register 2.12.3 VDP VITC Data Register2.12.5 VDP V-Chip TV Rating Block 2 Register 80 0530h2.12.7 VDP V-CHIP MPAA Rating Data Register 2.12.6 VDP V-Chip TV Rating Block 3 RegisterTV-G TV-Y72.12.8 VDP General Line Mode and Line Address Register 2.12.9 VDP VPS/Gemstar Data Register VPS Read onlyGemstar Read only Interrupt Configuration Register 2.12.10 Analog Output Control 2 Register2.12.11 3.2.1 Crystal Specifications Electrical Specifications3.1 Absolute Maximum Ratings† 3.2 Recommended Operating Conditions3.3.1 DC Electrical Characteristics see Note 3.3 Electrical Characteristics3.3.2 Analog Processing and A/D Converters 3.3.2.1 Fs = 30 MSPS for CH1, CH23.3.3.1 Clocks, Video Data, Sync Timing 3.3.3 Timing3.3.3.2 I2C Host Port Timing Figure 3−1. Clocks, Video Data, and Sync TimingElectrical Specifications TVP5147M1PFPSLES140A-March 4.1.2 Recommended Settings 4 Example Register Settings4.2.2 Recommended Settings 4.1 Example4.3.1 4.3.2 Recommended SettingsExample AssumptionsI2C register address 00h Example Register Settings TVP5147M1PFPSLES140A-March 5 Application Information 5.1 Application ExampleFigure 5−1. Example Application Circuit 5.2 Designing With PowerPADt Devices PACKAGING INFORMATION PACKAGE OPTION ADDENDUMPage