VDP TTX Filter Control Register | Texas Instruments TVP5147M1PFP

Functional Description

2.11.67 VDP TTX Filter Control Register

Subaddress		BBh

Default		00h

7	6		5	4	3	2	1	0

	Reserved			Filter logic [1:0]		Mode	TTX filter 2 enable	TTX filter 1 enable

Filter logic [1:0]: Allow different logic to be applied when combining the decision of filter 1 and filter 2 as follows:

00 = NOR (default)

01 = NAND

10 = OR

11 = AND

Mode: indicates which teletext mode is in use.

0 = Teletext filter applies to 2 header bytes (default) 1 = Teletext filter applies to 5 header bytes

TTX filter 2 enable: provides for enabling the teletext filter function within the VDP.

0 = Disabled (default)

1 = Enabled

TTX filter 1 enable: provides for enabling the teletext filter function within the VDP.

0 = Disabled (default)

1 = Enabled

If the filter matches or if the filter mask is all 0s, then a true result is returned.

TVP5147M1PFP

SLES140A—March 2007

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Texas Instruments TVP5147M1PFP manual VDP TTX Filter Control Register

TVP5147M1PFP specifications

The Texas Instruments TVP5147M1PFP is a versatile video decoder that stands out in the realm of analog video processing. This device is particularly designed for high-quality video applications, making it an excellent choice for a variety of consumer and professional electronics that require reliable video decoding capabilities.

One of the main features of the TVP5147 is its ability to decode multiple video formats, including NTSC, PAL, and SECAM. This flexibility allows the decoder to seamlessly interface with various video sources from different geographic regions, providing a global solution for video applications. The TVP5147 includes advanced synchronization features, ensuring it can effectively handle video signals that may vary in timing and quality.

The device is equipped with a sophisticated 10-bit analog-to-digital converter (ADC), which enhances the precision and clarity of the digital video output. This high-resolution capability allows for improved color accuracy and detail, leading to a more lifelike video representation. Additionally, the TVP5147 utilizes advanced digital processing technologies, including noise reduction and image enhancement features, contributing to outstanding image quality even in less than ideal input conditions.

Another notable characteristic of the TVP5147M1PFP is its support for various output formats, including ITU-R BT.601 and 656, which facilitates easy integration into different systems. The device can also provide various output resolutions, catering to the needs of diverse applications ranging from standard definition to high definition displays.

In terms of connectivity, the TVP5147 offers multiple input options, including composite video, S-video, and component video interfaces. This versatility ensures that it can accommodate a wide range of video sources, from traditional VHS players to modern digital cameras. Furthermore, the integrated video control features allow for easy adjustment of parameters such as brightness, contrast, and saturation.

The power consumption of the TVP5147M1PFP is optimized for low-energy applications while maintaining high performance, making it suitable for battery-powered devices and energy-efficient designs. Overall, the Texas Instruments TVP5147M1PFP is an exceptional video decoder that blends flexibility, high quality, and advanced technology, making it a preferred choice for video processing in numerous consumer and industrial applications. Its combination of features ensures reliable performance and high-quality output, fulfilling the demands of modern multimedia environments.

Contents

Data Manual Important Notice Contents Section 11.11 Section 11.59 Example List of Illustrations List of Tables Introduction Detailed Functionality Ordering Information TVP5147M1 ApplicationsRelated Products Packaged Devices Functional Block Diagram Terminal Assignments PFP Package TOP View −1. Terminal Functions Miscellaneous SignalsTerminal Functions Terminal Description Name Number Sync Signals VS/VBLK/GPIO Introduction PGA Video Input Switch ControlAnalog Processing and A/D Converters ADC Analog Video Output Analog Input ClampingAutomatic Gain Control 5 A/D Converters 1 2⋅ Decimation Filter Digital Video ProcessingComposite Processor NTSC/PAL CVBS/C −50 −60 −70 −10 − dB −20−30 −40 −10 Color Transient Improvement Luminance ProcessingOUT Real-Time Control RTC Clock CircuitsOutput Formatter Terminal Separate Syncs−1. Output Format Name Number FID Vblk Line 525 First Field Video VS StartVblk Start 622 623 624 625 First Field Video VS Start Vblk Start 23 24 Vblk Stop 336 337 Horizontal Blanking Cb0 Cr0 HS Start HS Stop Avid Stop Dataclk = 2⋅ Pixel Clock ModeAvid Start −15. Horizontal Synchronization Signals for 20-Bit 422 Mode Avid Stop Dataclk = 1⋅ Pixel Clock Mode −3. EAV and SAV Sequence Embedded SyncsI2C Host Interface D9 MSB 2 I2C Operation Reset and I2C Bus Address SelectionVbus Access −4. I 2C Host Interface Terminal Description Vbus HostI2C WSS Vitc −6. Supported VBI System VBI Data ProcessorVBI System Standard Line Number Number of Bytes Byte Description VBI Fifo and Ancillary Data in Video Stream−7. Ancillary Data Format and Sequence LSB VBI Raw Data Output Reset and Initialization−9. Reset Sequence −8. VBI Raw Data Output Format Internal Control Registers Adjusting External SyncsRegister Name 2C Subaddress Default −10. I 2C Register Summary Vblk start line V bit control 75h 12h VCR trick mode control 76h −11. Vbus Register Summary Register Definitions −12. Analog Channel and Video Mode SelectionMode Inputs Selected Input Select Output HEX Input Select Register Video Standard Register AFE Gain Control RegisterCvbs and S-Video Component Video Autoswitch Mask Register Operation Mode RegisterSubaddress 03h Default 00h Color Killer Register Luminance Processing Control 1 Register Luminance Processing Control 3 Register Subaddress 08h Default 02h Reserved Trap filter selectLuminance Processing Control 2 Register Luminance Brightness Register Chroma Hue Register Luminance Contrast RegisterChrominance Saturation Register Chrominance Processing Control 1 Register Avid Start Pixel Register Subaddress 0Eh DefaultChrominance Processing Control 2 Register WCF Hsync Stop Pixel Register Avid Stop Pixel RegisterHsync Start Pixel Register Vsync Start Line Register Vblk Start Line Register CTI Delay RegisterVsync Stop Line Register Vblk Stop Line Register CTI Control Register Subaddress 2Eh Default 00h CTI coring CTI gainSync Control Register Output Formatter 2 Register Subaddress 33h Default 40hOutput Formatter 1 Register CbCr code Reserved Output Formatter 3 Register Output Formatter 4 Register Output Formatter 5 Register Output Formatter 6 Register Subaddress 39h Default 00hClear Lost Lock Detect Register Status 1 Register Read only Color killed Status 2 RegisterAGC Gain Status Register Subaddress 3Ch Fine gain 3Dh Coarse gain Video Standard Status Register Gpio Input 1 Register Gpio Input 2 Register Glco FID AFE Coarse Gain for CH 1 Register Subaddress 46h Default 20h Cgain 1 ReservedSubaddress 47h Default 20h Cgain 2 Reserved AFE Coarse Gain for CH 2 Register AFE Coarse Gain for CH 3 Register Subaddress 48h Default 20h Cgain 3 ReservedSubaddress 49h Default 20h Cgain 4 Reserved AFE Coarse Gain for CH 4 Register AFE Fine Gain for YChroma Register AFE Fine Gain for Pb RegisterAFE Fine Gain for Pr Register Field ID Control Register Subaddress 57h Default 00hAFE Fine Gain for CVBSLuma Register FID control Reg 69h Reg 75h Mode Standard LPF Nonstandard LPF Bit Subaddress 69h Default 00hBit mode Bit and V-bit Control 1 Register AGC Decrement Speed Control Register Back-End AGC Control RegisterROM Version Register AGC White Peak Processing Register Subaddress 74h Default 00h Luma peak aLuma peak B Composite peak V Bit Control Register Lines per frame Bit Horizontal Shake Increment Register VCR Trick Mode Control RegisterAGC Increment Delay Register AGC Increment Speed Register Chip ID LSB Register Analog Output Control 1 RegisterChip ID MSB Register Cpll Speed Control Register Status Request Register AGC Decrement Delay RegisterVertical Line Count Register VDP TTX Filter And Mask Registers VDP TTX Filter Control Register Filter VDP Fifo Word Count RegisterNibble Pass VDP Fifo Output Control Register VDP Fifo Reset RegisterVDP Fifo Interrupt Threshold Register VDP Line Number Interrupt Register VDP Line Start Register VDP Global Line Mode RegisterVDP Pixel Alignment Register VDP Line Stop Register Vbus Data Access With No Vbus Address Increment Register VDP Full Field Enable RegisterVDP Full Field Mode Register Vbus Data Access With Vbus Address Increment Register Interrupt Raw Status 0 Register Vbus Address Access RegisterFifo Read Data Register Fifo Thrs TTX WSS VPS Vitc CC F2 CC F1 Reserved Lock Interrupt Raw Status 1 RegisterInterrupt Status 0 Register Fifo full Interrupt Status 1 Register Interrupt Mask 0 Register Interrupt Mask 1 Register Subaddress F5h Default 00hInterrupt Clear 0 Register Subaddress F7h Default 00h Interrupt Clear 1 Register VDP WSS Data Register Vbus Register DefinitionsVDP Closed Caption Data Register Subaddress Byte VDP V-Chip TV Rating Block 1 Register VDP Vitc Data RegisterVDP V-Chip TV Rating Block 2 Register None VDP V-Chip TV Rating Block 3 RegisterVDP V-CHIP Mpaa Rating Data Register TV-PG VDP General Line Mode and Line Address Register Default line mode = FFh, address = 00h VDP VPS/Gemstar Data Register VPS Read only Interrupt Configuration Register Analog Output Control 2 Register Absolute Maximum Ratings† Crystal SpecificationsCrystal Specifications MIN NOM MAX Unit Recommended Operating Conditions Analog Processing and A/D Converters Electrical CharacteristicsDC Electrical Characteristics see Note Parameter Test Conditions MIN TYP MAX Unit VOH VOL TimingDataclk AVID, VS, HS, FID VC1 SDA VC0 SCL Electrical Specifications Example Recommended SettingsAssumptions Assumptions Example Register Settings Example Register Settings Application Example −1. Example Application Circuit Designing With PowerPADt Devices MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page