Texas Instruments TVP5147M1PFP manual V bit control 75h 12h VCR trick mode control 76h

Functional Description

Table 2−10. I 2C Register Summary (Continued)

REGISTER NAME	I2C SUBADDRESS	DEFAULT	R/W
F and V bit control	75h	12h	R/W
VCR trick mode control	76h	8Ah	R/W
Horizontal shake increment	77h	64h	R/W
AGC increment speed	78h	05h	R/W
AGC increment delay	79h	1Eh	R/W
Reserved	7Ah−7Eh
Analog output control 1	7Fh	00h	R/W
Chip ID MSB	80h	51h	R
Chip ID LSB	81h	47h	R
Reserved	82h
CPLL speed control	83h	09h	R/W
Reserved	84h−96h
Status request	97h	00h	R/W
Reserved	98h−99h
Vertical line count	9Ah−9Bh		R
Reserved	9Ch−9Dh
AGC decrement delay	9Eh	00h	R/W
Reserved	9Fh−B0h
VDP TTX filter 1 mask 1	B1h	00h	R/W
VDP TTX filter 1 mask 2	B2h	00h	R/W
VDP TTX filter 1 mask 3	B3h	00h	R/W
VDP TTX filter 1 mask 4	B4h	00h	R/W
VDP TTX filter 1 mask 5	B5h	00h	R/W
VDP TTX filter 2 mask 1	B6h	00h	R/W
VDP TTX filter 2 mask 2	B7h	00h	R/W
VDP TTX filter 2 mask 3	B8h	00h	R/W
VDP TTX filter 2 mask 4	B9h	00h	R/W
VDP TTX filter 2 mask 5	BAh	00h	R/W
VDP TTX filter control	BBh	00h	R/W
VDP FIFO word count	BCh		R
VDP FIFO interrupt threshold	BDh	80h	R/W
Reserved	BEh
VDP FIFO reset	BFh	00h	R/W
VDP FIFO output control	C0h	00h	R/W
VDP line number interrupt	C1h	00h	R/W
VDP pixel alignment	C2h−C3h	01Eh	R/W
Reserved	C4h−D5h
VDP line start	D6h	06h	R/W
VDP line stop	D7h	1Bh	R/W
VDP global line mode	D8h	FFh	R/W
VDP full field enable	D9h	00h	R/W
VDP full field mode	DAh	FFh	R/W
Reserved	DBh−DFh

NOTE: R = Read only

W = Write only

R/W = Read and write

Reserved register addresses must not be written to.

SLES140A—March 2007 TVP5147M1PFP 29