Manuals / Texas Instruments / TV and Video / DVD Player

Texas Instruments TVP5147M1PFP manual Reset and I2C Bus Address Selection, 2.6.2 I2C Operation

Models: TVP5147M1PFP

1 100

Download 100 pages 24.7 Kb

Page 30

Table 2−4. I 2C Host Interface Terminal Description

Functional Description

Table 2−4. I 2C Host Interface Terminal Description

SIGNAL	TYPE	DESCRIPTION

I2CA	I	Slave address selection

SCL	I	Input clock line

SDA	I/O	Input/output data line

2.6.1 Reset and I2C Bus Address Selection

The TVP5147M1 decoder can respond to two possible chip addresses. The address selection is made at reset by an externally supplied level on the I2CA terminal. The TVP5147M1 decoder samples the level of terminal 37 at power up or at the trailing edge of RESETB and configures the I2C bus address bit A0. The I2CA terminal has an internal pulldown resistor to pull the terminal low to set a zero.

Table 2−5. I 2C Address Selection

A6	A5	A4	A3	A2	A1	A0 (I2CA)	R/W	HEX

1	0	1	1	1	0	0 (default)	1/0	B9/B8

1	0	1	1	1	0	1 †	1/0	BB/BA

†If terminal 37 is strapped to DVDD via a 2.2-kΩresistor, I2C device address A0 is set to 1.

2.6.2 I2C Operation

Data transfers occur using the following illustrated formats.

S

10111000

ACK

Subaddress

ACK

Send data

ACK

P

Read from I2C control registers

S

10111000 ACK

Subaddress

ACK

S

10111001

ACK

Receive data

NAK

P

S = I2C bus start condition P = I2C bus stop condition

ACK = Acknowledge generated by the slave

NAK = Acknowledge generated by the master, for multiple-byte read master with ACK each byte except last byte

Subaddress = Subaddress byte

Data = Data byte. If more than one byte of data is transmitted (read and write), the subaddress pointer is automatically incremented.

I2C bus address = Example shown that I2CA is in default mode. Write (B8h), read (B9h)

2.6.3 VBUS Access

The TVP5147M1 decoder has additional internal registers accessible through an indirect access to an internal 24-bit address wide VBUS. Figure 2−17 shows the VBUS register access.

22

TVP5147M1PFP

SLES140A—March 2007

Image 30

Texas Instruments TVP5147M1PFP manual Reset and I2C Bus Address Selection, 2.6.2 I2C Operation, VBUS Access

Contents

Data Manual Digital Audio VideoSLES140A MarchIMPORTANT NOTICE ProductsApplications Contents IntroductionJuly 3 Electrical Specifications ContentsExample Register Settings Application InformationList of Illustrations TitlePage List of Tables TitlePage 1 Introduction 1.1 Detailed Functionality 1.2 TVP5147M1 Applications 1.3 Related Products1.4 Ordering Information 1.5 Functional Block Diagram Figure 1−1. Functional Block DiagramFigure 1−2. Terminal Assignments Diagram 1.6 Terminal Assignments1.7 Terminal Functions Table 1−1. Terminal FunctionsTable 1−1. Terminal Functions Continued Power SuppliesIntroduction TVP5147M1PFPSLES140A-March 2.1 Analog Processing and A/D Converters 2.1.1 Video Input Switch Control2 Functional Description Figure 2−1. Analog Processors and A/D Converters2.1.4 Analog Video Output 2.1.2 Analog Input Clamping2.1.3 Automatic Gain Control 2.1.5 A/D Converters2.2.1 2⋅ Decimation Filter Figure 2−2. Digital Video Processing Block Diagram2.2 Digital Video Processing 2.2.2 Composite ProcessorFigure 2−3. Composite and S-Video Processing Block Diagram 2.2.2.1 Color Low-Pass FilterFigure 2−4. Color Low-Pass Filter Frequency Response Characteristics, NTSC/PAL ITU-R BT.601 Sampling2.2.2.2 Y/C Separation Figure 2−5. Color Low-Pass Filter With Filter2.2.4 Color Transient Improvement Figure 2−8. Luminance Edge-Enhancer Peaking Block Diagram2.2.3 Luminance Processing Figure 2−9. Peaking Filter Response NTSC/PAL ITU-R BT.601 Sampling2.4 Real-Time Control RTC Figure 2−10. Reference Clock Configurations2.3 Clock Circuits 2.5 Output Formatter2.5.1 Separate Syncs Table 2−1. Output FormatFigure 2−12. Vertical Synchronization Signals for 525-Line System NOTE Line numbering conforms to ITU-R BT.470Figure 2−13. Vertical Synchronization Signals for 625-Line System Functional DescriptionFigure 2−14. Horizontal Synchronization Signals for 10-Bit 422 Mode NTSCNOTE ITU-R BT.656 10-bit 422 timing with 2⋅ pixel clock reference Figure 2−15. Horizontal Synchronization Signals for 20-Bit 422 Mode Figure 2−16. VSYNC Position With Respect to HSYNC 2.5.2 Embedded Syncs2.6 I2C Host Interface Table 2−3. EAV and SAV Sequence2.6.2 I2C Operation 2.6.1 Reset and I2C Bus Address Selection2.6.3 VBUS Access Table 2−4. I 2C Host Interface Terminal DescriptionACK = Acknowledge generated by the slave Figure 2−17. VBUS AccessNOTE Examples use default I2C address NAK = No acknowledge generated by the master2.7 VBI Data Processor Table 2−6. Supported VBI System2.7.1 VBI FIFO and Ancillary Data in Video Stream Table 2−7. Ancillary Data Format and SequenceFigure 2−18. Reset Timing 2.8 Reset and InitializationTable 2−9. Reset Sequence 2.7.2 VBI Raw Data Output2.9 Adjusting External Syncs 2.10 Internal Control RegistersTable 2−10. I 2C Register Summary Table 2−10. I 2C Register Summary Continued 84h−96h Table 2−10. I 2C Register Summary Continued7Ah−7Eh 98h−99hTable 2−11. VBUS Register Summary Table 2−10. I 2C Register Summary ContinuedE3h−E7h 2.11 Register Definitions 2.11.1 Input Select RegisterTable 2−12. Analog Channel and Video Mode Selection CVBS and S-Video 2.11.2 AFE Gain Control Register2.11.3 Video Standard Register Component Video2.11.5 Autoswitch Mask Register 2.11.4 Operation Mode Register2.11.6 Color Killer Register 2.11.7 Luminance Processing Control 1 RegisterLuminance Brightness Register 2.11.8 Luminance Processing Control 2 Register2.11.9 Luminance Processing Control 3 Register 2.11.102.11.13 Chroma Hue Register 2.11.11 Luminance Contrast Register2.11.12 Chrominance Saturation Register 2.11.14 Chrominance Processing Control 1 Register2.11.15 Chrominance Processing Control 2 Register 2.11.16 AVID Start Pixel Register2.11.19 HSYNC Stop Pixel Register 2.11.17 AVID Stop Pixel Register2.11.18 HSYNC Start Pixel Register 2.11.20 VSYNC Start Line Register2.11.22 VBLK Start Line Register CTI Delay Register2.11.21 VSYNC Stop Line Register 2.11.23 VBLK Stop Line Register2.11.25 CTI Control RegisterSync Control Register 2.11.262.11.27 Output Formatter 1 Register 2.11.28 Output Formatter 2 Register2.11.29 Output Formatter 3 Register 2.11.30 Output Formatter 4 Register 2.11.31 Output Formatter 5 Register 2.11.32 Output Formatter 6 Register 2.11.33 Clear Lost Lock Detect Register2.11.34 Status 1 Register Signal present 2.11.35 Status 2 Register2.11.36 AGC Gain Status Register Weak signal detectionAutoswitch 2.11.37 Video Standard Status Register2.11.38 GPIO Input 1 Register Video standard2.11.39 GPIO Input 2 Register AVID2.11.40 AFE Coarse Gain for CH 1 Register 2.11.41 AFE Coarse Gain for CH 2 Register2.11.42 AFE Coarse Gain for CH 3 Register 2.11.43 AFE Coarse Gain for CH 4 Register2.11.44 AFE Fine Gain for Pb Register 2.11.45 AFE Fine Gain for YChroma Register2.11.46 AFE Fine Gain for Pr Register 2.11.47 AFE Fine Gain for CVBSLuma Register 2.11.48 Field ID Control Register656 version 2.11.49 F-bit and V-bit Control 1 Register 2.11.50 Back-End AGC Control Register 2.11.51 AGC Decrement Speed Control Register2.11.52 ROM Version Register 2.11.53 AGC White Peak Processing Register Lines per frame 2.11.54 F and V Bit Control RegisterF and F bit2.11.56 Horizontal Shake Increment Register 2.11.58 AGC Increment Delay Register2.11.55 VCR Trick Mode Control Register 2.11.57 AGC Increment Speed Register2.11.61 Chip ID LSB Register 2.11.59 Analog Output Control 1 Register2.11.60 Chip ID MSB Register 2.11.62 CPLL Speed Control Register2.11.64 Vertical Line Count Register 2.11.65 AGC Decrement Delay RegisterStatus Request Register 2.11.632.11.66 VDP TTX Filter And Mask Registers 2.11.67 VDP TTX Filter Control Register 2.11.68 VDP FIFO Word Count Register Figure 2−19. Teletext Filter Function2.11.71 VDP FIFO Output Control Register 2.11.70 VDP FIFO Reset Register2.11.69 VDP FIFO Interrupt Threshold Register 2.11.72 VDP Line Number Interrupt Register2.11.75 VDP Line Stop Register 2.11.73 VDP Pixel Alignment Register2.11.74 VDP Line Start Register 2.11.76 VDP Global Line Mode Register2.11.80 VBUS Data Access With VBUS Address Increment Register 2.11.77 VDP Full Field Enable Register2.11.79 VBUS Data Access With No VBUS Address Increment Register 2.11.78 VDP Full Field Mode Register2.11.83 Interrupt Raw Status 0 Register 2.11.82 VBUS Address Access Register2.11.81 FIFO Read Data Register FIFO THRSMacrovision status changed 2.11.84 Interrupt Raw Status 1 Register2.11.85 Interrupt Status 0 Register Standard changed2.11.86 Interrupt Status 1 Register 2.11.87 Interrupt Mask 0 Register 2.11.88 Interrupt Mask 1 Register 2.11.89 Interrupt Clear 0 Register2.11.90 Interrupt Clear 1 Register 2.12 VBUS Register Definitions 2.12.1 VDP Closed Caption Data Register2.12.2 VDP WSS Data Register 2.12.5 VDP V-Chip TV Rating Block 2 Register 2.12.3 VDP VITC Data Register2.12.4 VDP V-Chip TV Rating Block 1 Register 80 0530hTV-G 2.12.6 VDP V-Chip TV Rating Block 3 Register2.12.7 VDP V-CHIP MPAA Rating Data Register TV-Y72.12.8 VDP General Line Mode and Line Address Register 2.12.9 VDP VPS/Gemstar Data Register VPS Read onlyGemstar Read only Interrupt Configuration Register 2.12.10 Analog Output Control 2 Register2.12.11 3.1 Absolute Maximum Ratings† Electrical Specifications3.2.1 Crystal Specifications 3.2 Recommended Operating Conditions3.3.2 Analog Processing and A/D Converters 3.3 Electrical Characteristics3.3.1 DC Electrical Characteristics see Note 3.3.2.1 Fs = 30 MSPS for CH1, CH23.3.3.2 I2C Host Port Timing 3.3.3 Timing3.3.3.1 Clocks, Video Data, Sync Timing Figure 3−1. Clocks, Video Data, and Sync TimingElectrical Specifications TVP5147M1PFPSLES140A-March 4.2.2 Recommended Settings 4 Example Register Settings4.1.2 Recommended Settings 4.1 ExampleExample 4.3.2 Recommended Settings4.3.1 AssumptionsI2C register address 00h Example Register Settings TVP5147M1PFPSLES140A-March 5 Application Information 5.1 Application ExampleFigure 5−1. Example Application Circuit 5.2 Designing With PowerPADt Devices PACKAGE OPTION ADDENDUM PACKAGING INFORMATIONPage