Texas Instruments TVP5147M1PFP manual Timing, Dataclk AVID, VS, HS, FID, Voh Vol, VC1 SDA VC0 SCL

Electrical Specifications

3.3.3 Timing

3.3.3.1Clocks, Video Data, Sync Timing

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
		(see NOTE 1)
	Duty cycle DATACLK		45%	50%	55%
t1	High time, DATACLK			18.5		ns
t2	Low time, DATACLK			18.5		ns
t3	Fall time, DATACLK	90% to 10%			4	ns
t4	Rise time, DATACLK	10% to 90%			4	ns
t5	Output delay time				10	ns

NOTE 1: CL = 15 pF

DATACLK

Y, C, AVID, VS, HS, FID

t1

Valid Data

t2

t3 t4

Valid Data

t5

VOH

VOL

VOH

VOL

Figure 3−1. Clocks, Video Data, and Sync Timing

3.3.3.2I2C Host Port Timing

	PARAMETER	TEST CONDITIONS	MIN	TYP MAX	UNIT
t1	Bus free time between STOP and START		1.3		∝s
t2	Data hold time		0	0.9	∝s
t3	Data setup time		100		ns
t4	Setup time for a (repeated) START condition		0.6		∝s
t5	Setup time for a STOP condition		0.6		ns
t6	Hold time for a (repeated) START condition		0.6		∝s
t7	Rise time VC1(SDA) and VC0(SCL) signal			250	ns
t8	Fall time VC1(SDA) and VC0(SCL) signal			250	ns
Cb	Capacitive load for each bus line			400	pF
fI2C	I2C clock frequency			400	kHz
	Stop Start			Stop

VC1 (SDA)

t1

VC0 (SCL)

Data
t6	t		t3	t6	t
t7	2	t	t4		5
	Change		8

Data

Figure 3−2. I 2C Host Port Timing

SLES140A—March 2007 TVP5147M1PFP 81