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Texas Instruments TVP5147M1PFP manual VSYNC Stop Line Register, VBLK Start Line Register, 2.11.24

Models: TVP5147M1PFP

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2.11.21 VSYNC Stop Line Register

Functional Description

2.11.21 VSYNC Stop Line Register

Subaddress		20h−21h

Default		007h

Subaddress		7		6	5		4	3	2	1	0

20h							VSYNC stop [7:0]

21h						Reserved				VSYNC stop [9:8]

VSYNC stop [9:0]: This is an absolute line number. The TVP5147M1 decoder updates the VSYNC stop only when the VSYNC stop MSB is written to. If the user changes these registers, the TVP5147M1 decoder retains values in different modes until this decoder resets.

NTSC: default 007h

PAL: default 004h

2.11.22 VBLK Start Line Register

Subaddress		22h−23h

Default		001h

Subaddress		7		6	5		4	3	2	1	0

22h							VBLK start [7:0]

23h						Reserved				VBLK start [9:8]

VBLK start [9:0]: This is an absolute line number. The TVP5147M1 decoder updates the VBLK start line only when the VBLK start MSB is written to. If the user changes these registers, the TVP5147M1 decoder retains

values in different modes until this resets		(see Section 2.11.16)
NTSC: default 001h	PAL: default 623	(26Fh)

2.11.23 VBLK Stop Line Register

Subaddress		24h−25h

Default		015h

Subaddress		7		6	5		4	3	2	1	0

24h							VBLK stop [7:0]

25h						Reserved				VBLK stop [9:8]

VBLK stop [9:0]: This is an absolute line number. The TVP5147M1 decoder updates the VBLK stop only when the VBLK stop MSB is written to. If the user changes these registers, then the TVP5147M1 decoder retains values in different modes until this device resets (see Section 2.11.16).

NTSC: default 21 (015h)

PAL: default 23 (017h)

2.11.24	CTI Delay Register
Subaddress			2Dh

Default			00h

7			6		5	4	3	2	1	0

					Reserved				CTI delay [2:0]

CTI delay [2:0]: Sets the delay of the Y channel with respect to Cb/Cr in the CTI block

011 = 3-pixel delay

001 = 1-pixel delay

000 = 0 delay (default)

111 = −1-pixel delay

100 = −4-pixel delay

SLES140A—March 2007

TVP5147M1PFP

39

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Texas Instruments TVP5147M1PFP manual VSYNC Stop Line Register, VBLK Start Line Register, VBLK Stop Line Register, 2.11.24

Contents

March Digital Audio VideoSLES140A Data ManualApplications IMPORTANT NOTICEProducts Introduction ContentsJuly Contents 3 Electrical SpecificationsApplication Information Example Register SettingsPage List of IllustrationsTitle Page List of TablesTitle 1 Introduction 1.1 Detailed Functionality 1.4 Ordering Information 1.2 TVP5147M1 Applications1.3 Related Products Figure 1−1. Functional Block Diagram 1.5 Functional Block Diagram1.6 Terminal Assignments Figure 1−2. Terminal Assignments DiagramTable 1−1. Terminal Functions 1.7 Terminal FunctionsPower Supplies Table 1−1. Terminal Functions ContinuedSLES140A-March IntroductionTVP5147M1PFP Figure 2−1. Analog Processors and A/D Converters 2.1.1 Video Input Switch Control2 Functional Description 2.1 Analog Processing and A/D Converters2.1.5 A/D Converters 2.1.2 Analog Input Clamping2.1.3 Automatic Gain Control 2.1.4 Analog Video Output2.2.2 Composite Processor Figure 2−2. Digital Video Processing Block Diagram2.2 Digital Video Processing 2.2.1 2⋅ Decimation Filter2.2.2.1 Color Low-Pass Filter Figure 2−3. Composite and S-Video Processing Block DiagramFigure 2−5. Color Low-Pass Filter With Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling2.2.2.2 Y/C Separation Figure 2−4. Color Low-Pass Filter Frequency ResponseFigure 2−9. Peaking Filter Response NTSC/PAL ITU-R BT.601 Sampling Figure 2−8. Luminance Edge-Enhancer Peaking Block Diagram2.2.3 Luminance Processing 2.2.4 Color Transient Improvement2.5 Output Formatter Figure 2−10. Reference Clock Configurations2.3 Clock Circuits 2.4 Real-Time Control RTCTable 2−1. Output Format 2.5.1 Separate SyncsNOTE Line numbering conforms to ITU-R BT.470 Figure 2−12. Vertical Synchronization Signals for 525-Line SystemFunctional Description Figure 2−13. Vertical Synchronization Signals for 625-Line SystemNOTE ITU-R BT.656 10-bit 422 timing with 2⋅ pixel clock reference Figure 2−14. Horizontal Synchronization Signals for 10-Bit 422 ModeNTSC Figure 2−15. Horizontal Synchronization Signals for 20-Bit 422 Mode Table 2−3. EAV and SAV Sequence 2.5.2 Embedded Syncs2.6 I2C Host Interface Figure 2−16. VSYNC Position With Respect to HSYNCTable 2−4. I 2C Host Interface Terminal Description 2.6.1 Reset and I2C Bus Address Selection2.6.3 VBUS Access 2.6.2 I2C OperationNAK = No acknowledge generated by the master Figure 2−17. VBUS AccessNOTE Examples use default I2C address ACK = Acknowledge generated by the slaveTable 2−6. Supported VBI System 2.7 VBI Data ProcessorTable 2−7. Ancillary Data Format and Sequence 2.7.1 VBI FIFO and Ancillary Data in Video Stream2.7.2 VBI Raw Data Output 2.8 Reset and InitializationTable 2−9. Reset Sequence Figure 2−18. Reset TimingTable 2−10. I 2C Register Summary 2.9 Adjusting External Syncs2.10 Internal Control Registers Table 2−10. I 2C Register Summary Continued 98h−99h Table 2−10. I 2C Register Summary Continued7Ah−7Eh 84h−96hE3h−E7h Table 2−11. VBUS Register SummaryTable 2−10. I 2C Register Summary Continued Table 2−12. Analog Channel and Video Mode Selection 2.11 Register Definitions2.11.1 Input Select Register Component Video 2.11.2 AFE Gain Control Register2.11.3 Video Standard Register CVBS and S-Video2.11.4 Operation Mode Register 2.11.5 Autoswitch Mask Register2.11.7 Luminance Processing Control 1 Register 2.11.6 Color Killer Register2.11.10 2.11.8 Luminance Processing Control 2 Register2.11.9 Luminance Processing Control 3 Register Luminance Brightness Register2.11.14 Chrominance Processing Control 1 Register 2.11.11 Luminance Contrast Register2.11.12 Chrominance Saturation Register 2.11.13 Chroma Hue Register2.11.16 AVID Start Pixel Register 2.11.15 Chrominance Processing Control 2 Register2.11.20 VSYNC Start Line Register 2.11.17 AVID Stop Pixel Register2.11.18 HSYNC Start Pixel Register 2.11.19 HSYNC Stop Pixel Register2.11.23 VBLK Stop Line Register CTI Delay Register2.11.21 VSYNC Stop Line Register 2.11.22 VBLK Start Line Register2.11.26 CTI Control RegisterSync Control Register 2.11.252.11.28 Output Formatter 2 Register 2.11.27 Output Formatter 1 Register2.11.29 Output Formatter 3 Register 2.11.30 Output Formatter 4 Register 2.11.31 Output Formatter 5 Register 2.11.33 Clear Lost Lock Detect Register 2.11.32 Output Formatter 6 Register2.11.34 Status 1 Register Weak signal detection 2.11.35 Status 2 Register2.11.36 AGC Gain Status Register Signal presentVideo standard 2.11.37 Video Standard Status Register2.11.38 GPIO Input 1 Register AutoswitchAVID 2.11.39 GPIO Input 2 Register2.11.41 AFE Coarse Gain for CH 2 Register 2.11.40 AFE Coarse Gain for CH 1 Register2.11.43 AFE Coarse Gain for CH 4 Register 2.11.42 AFE Coarse Gain for CH 3 Register2.11.46 AFE Fine Gain for Pr Register 2.11.44 AFE Fine Gain for Pb Register2.11.45 AFE Fine Gain for YChroma Register 656 version 2.11.47 AFE Fine Gain for CVBSLuma Register2.11.48 Field ID Control Register 2.11.49 F-bit and V-bit Control 1 Register 2.11.52 ROM Version Register 2.11.50 Back-End AGC Control Register2.11.51 AGC Decrement Speed Control Register 2.11.53 AGC White Peak Processing Register F bit 2.11.54 F and V Bit Control RegisterF and Lines per frame2.11.57 AGC Increment Speed Register 2.11.58 AGC Increment Delay Register2.11.55 VCR Trick Mode Control Register 2.11.56 Horizontal Shake Increment Register2.11.62 CPLL Speed Control Register 2.11.59 Analog Output Control 1 Register2.11.60 Chip ID MSB Register 2.11.61 Chip ID LSB Register2.11.63 2.11.65 AGC Decrement Delay RegisterStatus Request Register 2.11.64 Vertical Line Count Register2.11.66 VDP TTX Filter And Mask Registers 2.11.67 VDP TTX Filter Control Register Figure 2−19. Teletext Filter Function 2.11.68 VDP FIFO Word Count Register2.11.72 VDP Line Number Interrupt Register 2.11.70 VDP FIFO Reset Register2.11.69 VDP FIFO Interrupt Threshold Register 2.11.71 VDP FIFO Output Control Register2.11.76 VDP Global Line Mode Register 2.11.73 VDP Pixel Alignment Register2.11.74 VDP Line Start Register 2.11.75 VDP Line Stop Register2.11.78 VDP Full Field Mode Register 2.11.77 VDP Full Field Enable Register2.11.79 VBUS Data Access With No VBUS Address Increment Register 2.11.80 VBUS Data Access With VBUS Address Increment RegisterFIFO THRS 2.11.82 VBUS Address Access Register2.11.81 FIFO Read Data Register 2.11.83 Interrupt Raw Status 0 RegisterStandard changed 2.11.84 Interrupt Raw Status 1 Register2.11.85 Interrupt Status 0 Register Macrovision status changed2.11.86 Interrupt Status 1 Register 2.11.87 Interrupt Mask 0 Register 2.11.89 Interrupt Clear 0 Register 2.11.88 Interrupt Mask 1 Register2.11.90 Interrupt Clear 1 Register 2.12.2 VDP WSS Data Register 2.12 VBUS Register Definitions2.12.1 VDP Closed Caption Data Register 80 0530h 2.12.3 VDP VITC Data Register2.12.4 VDP V-Chip TV Rating Block 1 Register 2.12.5 VDP V-Chip TV Rating Block 2 RegisterTV-Y7 2.12.6 VDP V-Chip TV Rating Block 3 Register2.12.7 VDP V-CHIP MPAA Rating Data Register TV-G2.12.8 VDP General Line Mode and Line Address Register Gemstar Read only 2.12.9 VDP VPS/Gemstar Data RegisterVPS Read only 2.12.11 Interrupt Configuration Register2.12.10 Analog Output Control 2 Register 3.2 Recommended Operating Conditions Electrical Specifications3.2.1 Crystal Specifications 3.1 Absolute Maximum Ratings†3.3.2.1 Fs = 30 MSPS for CH1, CH2 3.3 Electrical Characteristics3.3.1 DC Electrical Characteristics see Note 3.3.2 Analog Processing and A/D ConvertersFigure 3−1. Clocks, Video Data, and Sync Timing 3.3.3 Timing3.3.3.1 Clocks, Video Data, Sync Timing 3.3.3.2 I2C Host Port TimingSLES140A-March Electrical SpecificationsTVP5147M1PFP 4.1 Example 4 Example Register Settings4.1.2 Recommended Settings 4.2.2 Recommended SettingsAssumptions 4.3.2 Recommended Settings4.3.1 ExampleI2C register address 00h SLES140A-March Example Register SettingsTVP5147M1PFP Figure 5−1. Example Application Circuit 5 Application Information5.1 Application Example 5.2 Designing With PowerPADt Devices PACKAGING INFORMATION PACKAGE OPTION ADDENDUMPage