Gpio Input 2 Register, Glco FID | Texas Instruments TVP5147M1PFP

Functional Description

2.11.39 GPIO Input 2 Register

Subaddress

41h

Read only

7	6	5	4	3	2	1	0

GPIO	AVID	GLCO	VS	HS	FID	C_9	C_8

GPIO input terminal status:

0 = Input is a low.

1 = Input is a high.

AVID input terminal status:

0 = Input is a low.

1 = Input is a high.

GLCO input terminal status:

0 = Input is a low.

1 = Input is a high.

VS input terminal status:

0 = Input is a low.

1 = Input is a high.

HS input status:

0 = Input is a low.

1 = Input is a high.

FID input status:

0 = Input is a low.

1 = Input is a high.

C_x input status:

0 = Input is a low.

1 = Input is a high.

These status bits are only valid when terminals are used as input and its states updated at every line.

SLES140A—March 2007

TVP5147M1PFP

Page 57

Image 57

Texas Instruments TVP5147M1PFP manual Gpio Input 2 Register, Glco FID

TVP5147M1PFP specifications

The Texas Instruments TVP5147M1PFP is a versatile video decoder that stands out in the realm of analog video processing. This device is particularly designed for high-quality video applications, making it an excellent choice for a variety of consumer and professional electronics that require reliable video decoding capabilities.

One of the main features of the TVP5147 is its ability to decode multiple video formats, including NTSC, PAL, and SECAM. This flexibility allows the decoder to seamlessly interface with various video sources from different geographic regions, providing a global solution for video applications. The TVP5147 includes advanced synchronization features, ensuring it can effectively handle video signals that may vary in timing and quality.

The device is equipped with a sophisticated 10-bit analog-to-digital converter (ADC), which enhances the precision and clarity of the digital video output. This high-resolution capability allows for improved color accuracy and detail, leading to a more lifelike video representation. Additionally, the TVP5147 utilizes advanced digital processing technologies, including noise reduction and image enhancement features, contributing to outstanding image quality even in less than ideal input conditions.

Another notable characteristic of the TVP5147M1PFP is its support for various output formats, including ITU-R BT.601 and 656, which facilitates easy integration into different systems. The device can also provide various output resolutions, catering to the needs of diverse applications ranging from standard definition to high definition displays.

In terms of connectivity, the TVP5147 offers multiple input options, including composite video, S-video, and component video interfaces. This versatility ensures that it can accommodate a wide range of video sources, from traditional VHS players to modern digital cameras. Furthermore, the integrated video control features allow for easy adjustment of parameters such as brightness, contrast, and saturation.

The power consumption of the TVP5147M1PFP is optimized for low-energy applications while maintaining high performance, making it suitable for battery-powered devices and energy-efficient designs. Overall, the Texas Instruments TVP5147M1PFP is an exceptional video decoder that blends flexibility, high quality, and advanced technology, making it a preferred choice for video processing in numerous consumer and industrial applications. Its combination of features ensures reliable performance and high-quality output, fulfilling the demands of modern multimedia environments.

Contents

Data Manual Important Notice Contents Section 11.11 Section 11.59 Example List of Illustrations List of Tables Introduction Detailed Functionality Related Products TVP5147M1 ApplicationsOrdering Information Packaged Devices Functional Block Diagram PFP Package TOP View Terminal Assignments Terminal Functions Miscellaneous Signals−1. Terminal Functions Terminal Description Name Number VS/VBLK/GPIO Sync Signals Introduction Analog Processing and A/D Converters Video Input Switch ControlPGA ADC Automatic Gain Control Analog Input ClampingAnalog Video Output 5 A/D Converters Digital Video Processing 1 2⋅ Decimation FilterComposite Processor CVBS/C NTSC/PAL −30 −40 −10 − dB −20−50 −60 −70 −10 Luminance Processing Color Transient ImprovementOUT Clock Circuits Real-Time Control RTCOutput Formatter −1. Output Format Separate SyncsTerminal Name Number Line 525 First Field Video VS Start FID VblkVblk Start Vblk Start 23 24 Vblk Stop 336 337 622 623 624 625 First Field Video VS Start Avid Stop Dataclk = 2⋅ Pixel Clock Mode Horizontal Blanking Cb0 Cr0 HS Start HS StopAvid Start Avid Stop Dataclk = 1⋅ Pixel Clock Mode −15. Horizontal Synchronization Signals for 20-Bit 422 Mode I2C Host Interface Embedded Syncs−3. EAV and SAV Sequence D9 MSB Vbus Access Reset and I2C Bus Address Selection2 I2C Operation −4. I 2C Host Interface Terminal Description I2C HostVbus WSS Vitc VBI Data Processor −6. Supported VBI SystemVBI System Standard Line Number Number of Bytes −7. Ancillary Data Format and Sequence VBI Fifo and Ancillary Data in Video StreamByte Description LSB −9. Reset Sequence Reset and InitializationVBI Raw Data Output −8. VBI Raw Data Output Format Register Name 2C Subaddress Default Adjusting External SyncsInternal Control Registers −10. I 2C Register Summary Vblk start line V bit control 75h 12h VCR trick mode control 76h −11. Vbus Register Summary Mode Inputs Selected Input Select Output HEX −12. Analog Channel and Video Mode SelectionRegister Definitions Input Select Register AFE Gain Control Register Video Standard RegisterCvbs and S-Video Component Video Operation Mode Register Autoswitch Mask RegisterSubaddress 03h Default 00h Luminance Processing Control 1 Register Color Killer Register Luminance Processing Control 2 Register Subaddress 08h Default 02h Reserved Trap filter selectLuminance Processing Control 3 Register Luminance Brightness Register Chrominance Saturation Register Luminance Contrast RegisterChroma Hue Register Chrominance Processing Control 1 Register Chrominance Processing Control 2 Register Subaddress 0Eh DefaultAvid Start Pixel Register WCF Hsync Start Pixel Register Avid Stop Pixel RegisterHsync Stop Pixel Register Vsync Start Line Register Vsync Stop Line Register CTI Delay RegisterVblk Start Line Register Vblk Stop Line Register Subaddress 2Eh Default 00h CTI coring CTI gain CTI Control RegisterSync Control Register Output Formatter 1 Register Subaddress 33h Default 40hOutput Formatter 2 Register CbCr code Reserved Output Formatter 3 Register Output Formatter 4 Register Output Formatter 5 Register Subaddress 39h Default 00h Output Formatter 6 RegisterClear Lost Lock Detect Register Read only Status 1 Register AGC Gain Status Register Status 2 RegisterColor killed Subaddress 3Ch Fine gain 3Dh Coarse gain Gpio Input 1 Register Video Standard Status Register Glco FID Gpio Input 2 Register Subaddress 47h Default 20h Cgain 2 Reserved Subaddress 46h Default 20h Cgain 1 ReservedAFE Coarse Gain for CH 1 Register AFE Coarse Gain for CH 2 Register Subaddress 49h Default 20h Cgain 4 Reserved Subaddress 48h Default 20h Cgain 3 ReservedAFE Coarse Gain for CH 3 Register AFE Coarse Gain for CH 4 Register AFE Fine Gain for Pb Register AFE Fine Gain for YChroma RegisterAFE Fine Gain for Pr Register AFE Fine Gain for CVBSLuma Register Subaddress 57h Default 00hField ID Control Register FID control Bit mode Subaddress 69h Default 00hReg 69h Reg 75h Mode Standard LPF Nonstandard LPF Bit Bit and V-bit Control 1 Register Back-End AGC Control Register AGC Decrement Speed Control RegisterROM Version Register Subaddress 74h Default 00h Luma peak a AGC White Peak Processing RegisterLuma peak B Composite peak Lines per frame Bit V Bit Control Register AGC Increment Delay Register VCR Trick Mode Control RegisterHorizontal Shake Increment Register AGC Increment Speed Register Chip ID MSB Register Analog Output Control 1 RegisterChip ID LSB Register Cpll Speed Control Register AGC Decrement Delay Register Status Request RegisterVertical Line Count Register VDP TTX Filter And Mask Registers VDP TTX Filter Control Register Nibble VDP Fifo Word Count RegisterFilter Pass VDP Fifo Interrupt Threshold Register VDP Fifo Reset RegisterVDP Fifo Output Control Register VDP Line Number Interrupt Register VDP Pixel Alignment Register VDP Global Line Mode RegisterVDP Line Start Register VDP Line Stop Register VDP Full Field Mode Register VDP Full Field Enable RegisterVbus Data Access With No Vbus Address Increment Register Vbus Data Access With Vbus Address Increment Register Fifo Read Data Register Vbus Address Access RegisterInterrupt Raw Status 0 Register Fifo Thrs TTX WSS VPS Vitc CC F2 CC F1 Interrupt Status 0 Register Interrupt Raw Status 1 RegisterReserved Lock Fifo full Interrupt Status 1 Register Interrupt Mask 0 Register Subaddress F5h Default 00h Interrupt Mask 1 RegisterInterrupt Clear 0 Register Interrupt Clear 1 Register Subaddress F7h Default 00h VDP Closed Caption Data Register Vbus Register DefinitionsVDP WSS Data Register Subaddress Byte VDP Vitc Data Register VDP V-Chip TV Rating Block 1 RegisterVDP V-Chip TV Rating Block 2 Register VDP V-CHIP Mpaa Rating Data Register VDP V-Chip TV Rating Block 3 RegisterNone TV-PG Default line mode = FFh, address = 00h VDP General Line Mode and Line Address Register VPS Read only VDP VPS/Gemstar Data Register Analog Output Control 2 Register Interrupt Configuration Register Crystal Specifications MIN NOM MAX Unit Crystal SpecificationsAbsolute Maximum Ratings† Recommended Operating Conditions DC Electrical Characteristics see Note Electrical CharacteristicsAnalog Processing and A/D Converters Parameter Test Conditions MIN TYP MAX Unit Dataclk AVID, VS, HS, FID TimingVOH VOL VC1 SDA VC0 SCL Electrical Specifications Recommended Settings ExampleAssumptions Assumptions Example Register Settings Example Register Settings −1. Example Application Circuit Application Example Designing With PowerPADt Devices Orderable Device Status Package Pins Package Eco Plan MSL Peak TempQty Page