Contents
Revision History
Date | Revision | Description |
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May 2005 | 003 | Revised Table 1 and Table 9 |
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| Updated PCI Express operation information in Section 1.1 and |
October 2004 | 002 | Table 2 inSection 2.2. |
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| Removed L0s state information throughout manual. |
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March 2004 | 001 | Initial release |
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10 | Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual |