Intel 41210 manual Offset 3Eh BCTRL-Bridge Control Sheet 2

Page 89

 

 

 

 

Register Description

Table 54.

Offset 3Eh: BCTRL—Bridge Control (Sheet 2 of 2)

 

 

 

 

 

Bits

 

Type

Reset

Description

 

 

 

 

 

 

 

 

 

Master Abort Mode (MAM): This bit controls the bridge’s behavior when a master-abort (or

 

 

 

 

unsupported request) occurs on either interface. This bit does not affect the behavior when

 

 

 

 

the bridge forwards a UR completion from PCI Express* to master-abort on PCI-X.

 

 

 

 

0 = Do not report master-aborts. When a UR response is received from PCI Express* for

 

 

 

 

non-posted transactions, and when the secondary side is operating in conventional

5

 

RW

0b

PCI mode, the device returns FFFF FFFFh on reads and completes I/O writes

 

normally. For posted transactions, the data is discarded and no additional action is

 

 

 

 

 

 

 

 

taken.

 

 

 

 

1 = Report UR completions by signaling a target-abort on the secondary/peer interface

 

 

 

 

when operating in conventional PCI mode. The device returns

 

 

 

 

ERR_NONFATAL/ERR_FATAL messages for posted transactions initiated from PCI

 

 

 

 

Express*.

 

 

 

 

 

 

 

 

 

VGA 16-bit Decode: This bit enables the bridge to provide 16-bit decoding of VGA I/O

4

 

RW

0b

address precluding the decoding of VGA alias addresses every 1 KB. This bit requires the

 

 

 

 

VGA enable bit (bit 3 of this register) to be set to 1.

 

 

 

 

 

 

 

 

 

VGA Enable (VGAE): This bit modifies the response to VGA-compatible addresses. When

 

 

 

 

set to 1, the bridge forwards the following transactions from PCI Express*-to-PCI regardless

 

 

 

 

of the value of the I/O base and limit registers. The transactions are qualified by the memory

 

 

 

 

enable and I/O enable in the command register.

3

 

RW

0b

Memory addresses: 000A 0000h–000B FFFFh

 

I/O addresses: 3B0h–3BBh and 3C0h–3DFh. For the I/O addresses, bits[63:16] of the

 

 

 

 

 

 

 

 

address must be 0, and bits[15:10] of the address are ignored (aliased).

 

 

 

 

The same holds true from secondary accesses to the primary interface in reverse for

 

 

 

 

memory accesses and also for I/O when the upstream I/O enable bit is set in the BINIT

 

 

 

 

register, from secondary to primary.

 

 

 

 

 

 

 

 

 

ISA Enable (IE): This bit modifies the response by the bridge to ISA I/O addresses. This

 

 

 

 

function applies only to I/O addresses that are enabled by the I/O base and I/O limit

2

 

RW

0b

registers and are in the first 64 KB of PCI I/O space. When this bit is set, the bridge blocks

 

all forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in

 

 

 

 

each 1 KB block (offsets 100h to 3FFh). This bit has the reverse effect on I/O transfers

 

 

 

 

originating on the secondary bus when the upstream I/O enable bit is set in the BINIT

 

 

 

 

Register (“Offset FCh: BINIT—Bridge Initialization Register” on page 104).

 

 

 

 

 

 

 

 

 

SERR# Enable (SE): This bit controls the forwarding of secondary interface SERR#

 

 

 

 

assertions on the primary interface. When set, the bridge sends a PCI Express*

 

 

 

 

ERR_NONFATAL/ERR_FATAL cycle (based on Advanced Error capability’s PCI SERR

 

 

 

 

detected severity bit) when all of the following conditions are true:

1

 

RW

0b

• SERR# is asserted on the secondary interface.

 

 

 

 

• This bit is set.

 

 

 

 

• The SERR# detected mask bit in the Advanced Error capability is set.

 

 

 

 

• ERR_NONFATAL/ERR_FATAL messages are enabled to be sent.

 

 

 

 

 

 

 

 

 

Parity Error Response Enable (PERE): This bit controls the response to address and data

0

 

RW

0b

parity errors on the secondary interface. When the bit is cleared, the bridge must ignore any

 

parity errors that it detects and continue normal operation. The bridge must generate parity

 

 

 

 

 

 

 

 

even when parity error reporting is disabled.

 

 

 

 

 

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

89

Page 88 Page 90
Image 89
Page 88 Page 90
Contents Developer’s Manual Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Date Revision Description Revision HistoryIntroduction1 PCI Express* Interface FeaturesPCI-X Interface Features Jtag Power ManagementSMBus Interface On-Die Termination ODT Signal DescriptionAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 ODT SignalsADEVSEL# BDEVSEL# AFRAME# BFRAME# AGNT#50 BGNT#50PCI Express* Interface PCI Express* Interface PinsPERCOMP10 TotalPCI Bus Interface Two Instances PCI Interface Pins Sheet 1ADEVSEL# AIRDY#PCI Interface Pins Sheet 2 PCI Bus Interface 64-Bit Extension Two Interfaces PCI Interface Pins 64-Bit ExtensionsPCI Clock and Reset Pins Interrupt Interface Two Interfaces Interrupt Interface PinsAINTA# AINTB# AINTC# AINTD#Cfgretry Reset StrapsReset Strap Pins SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsNumber Description Voltage PinsThis page Intentionally Left Blank PCI-X Interface PCI Mode Pin/Strap EncodingInitialization PCI-X Initialization PatternTransactions Supported PCI ModePCI Transactions Supported Transaction Encoding1PCI-X Transactions Supported PCI-X ModeRead Transactions Delayed Configuration TransactionsPCI Lock CyclesEnd Point Source Transaction Termination DecodingPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface Attributes PCI-X Protocol Specifics2 4 GB and 4 K Page Crossover Wait StatesSplit Transactions ArbitrationFields Split Completion Abort RegistersBridgeM0 High Priority Group Lpg Low Priority B3173-01 Internal Arbitration SchemeHardware-Controlled Active State Power Management Power ManagementSoftware-Driven PCI-PM 1.1-Compatible Power Management PCI Bus Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank PCI-to-PCI Bridge a Configuration Space Addressable Space AccessPCI-to-PCI Bridge B Configuration Space Addressing5PCI Express* Configuration Access Configuration-Space AccessDevice Number Signal Used for Public/Private Secondary PCI DevicesAddressing Type 1 to Type 0 Translation PCI and PCI-X Type 0 Configuration Access from PCI-X InterfaceSMBus Configuration Access I/O Space Access MechanismO Forwarding Memory Space Access Mechanism Memory Forwarding Memory-Mapped I/O WindowOpaque Memory Window VGA AddressingPrefetchable Memory Window § § Upstream Transaction Ordering Transaction OrderingUpstream Transaction Ordering Row Pass ColumnDownstream Transaction Ordering Downstream Transaction OrderingRelaxed Ordering/No-Snoop Support INTx Routing Table Interrupt SupportLegacy Interrupt Sharing Interrupt Binding for Devices behind a Bridge Interrupt Routing for Devices behind a BridgeDevice Number on Secondary BusBit Value System Management Bus InterfaceSMBus Address Assignments SMBus Command Encoding SMBus CommandsInternal Command SMBus commandSMBus Status Byte Encoding ConfigurationInitialization Sequence Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Device Reset Clock and ResetClocking Clock DomainsPCI Express* Reset Mechanism PERST# Reset MechanismRSTIN# Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank PCI Errors Error HandlingPCI Express* Errors Termination of Completion Required Transactions Error TypesCompletion-Status Translation for Immediate Terminations PCI-X Termination PCI Express* CompletionSuccessful 00h PCI-X Split Termination Message PCI ExpressIndex PCI Express* Completion Status PCI Completion Split Termination on PCI Express* InterfacePERST# reset Register Nomenclature and Access AttributesRegister Description Bit Attribute DefinitionsConfiguration Registers Capptr PCI/PCI-X Compatible Configuration region0xFFF 0x300 0x100 0x40 0x00 B3174-02Legacy Configuration Space Byte Offset PCI Express* Extended Configuration SpaceRegister Offset 04h PCICMD-Command Register Sheet 1 Offset 04h PCICMD-Command RegisterReset Description Offset 00h ID-IdentifiersOffset 06h PSTS-Primary Device Status Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status Sheet 1 TypeOffset 06h PSTS-Primary Device Status Sheet 2 Offset 08h REVID-Revision IDOffset 08h REVID-Revision ID BitsOffset 09h CC-Class Code Offset 0Dh PMLT-Primary Master Latency TimerOffset 0Ch CLS-Cache-Line Size Offset 0Eh HEADTYP-Header TypeOffset 1Bh SMLT-Secondary Master Latency Timer Offset 1Bh SMLT-Secondary Master Latency TimerOffset 18h BNUM-Bus Numbers Offset 18h BNUM-Bus NumbersOffset 1Ch IOBL-I/O Base and Limit Offset 1Ch IOBL-I/O Base and LimitFFFh Support for 16-bit I/O addressing onlyOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary StatusOffset 20h MBL-Memory Base and Limit Offset 20h MBL-Memory Base and Limit3120 000h Must be less than this valueOffset 24h PMBL-Prefetchable Memory Base and Limit Bits Type Reset DescriptionOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 34h CAPP-Capabilities List Pointer Offset 3Ch INTR-Interrupt InformationOffset 3Eh BCTRL-Bridge Control Sheet 1 Offset 3Eh BCTRL-Bridge ControlOffset 3Eh BCTRL-Bridge Control Sheet 2 Offset 40h BCNF-Bridge Configuration Register Offset 40h BCNF-Bridge Configuration RegisterPeer Memory Read Enable Pmre Bit Maximum Number of Upstream Delayed TransactionsOffset 43h PCLKC-PCI Clock Control Offset 42h MTT-Multi-Transaction TimerOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 45h EXPNXTP-Next Item PointerOffset 46h EXPCAP-PCI Express* Capability Default DescriptionOffset 46h EXPCAP-PCI Express* Capability Bit MaxPayloadSize Offset 4Ch EXPDCTL-PCI Express* Device Control RegisterBit MaxReadRequestSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 4Eh EXPDSTS-PCI Express* Device Status RegisterOffset 50h EXPLCAP-PCI Express* Link Capabilities Register Offset 54h EXPLCTL-PCI Express* Link Control Register Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit LatencyOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 56h EXPLSTS-PCI Express* Link Status RegisterOffset 5Ch MSICAPID-PCI Express* MSI Capability Identifier Offset 5Eh MSIMC-PCI Express* MSI Message Control Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 60h MSIMA-PCI Express* MSI Message Address Offset 68h MSIMD-PCI Express* MSI Message DataOffset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management CapabilitiesOffset 73h PMDATA-Power Management Data Field Offset 70h PMPMCSR-Power Management Control/Status RegisterOffset 72h PMBSE-Power Management Bridge Support Extensions Offset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item PointerOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterAdvanced Error Reporting Extended Capability Version Number Power Budgeting Capability as the next capabilityID, indicating Advanced Error Reporting Capability When the configuration unit signals a completer abortOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskFlow Control Protocol Error Status Severity Unsupported Request Error Status SeverityData Link Protocol Error Severity Training Error Severity Not supportedOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask1270 Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header LogOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Sheet 1 Logs the header Sheet 2PCI Delayed Transaction Timer Expiry Mask Internal Bridge Data Error MaskPCI-X Uncorrectable Address Parity Error Detected Mask PCI-X Uncorrectable Attribute Parity Error Detected MaskPCI-X Detected Split Completion Master Abort Mask PCI-X Detected Target Abort Mask optional in specificationPCI Delayed Transaction Timer Expiry Severity Internal Bridge Data Error SeverityPCI-X Uncorrectable Address Parity Error Detected Severity PCI-X Uncorrectable Data Parity Error Detected SeverityRegister is cleared by the software writing a 1 to the bit Rwcs = Errnonfatal = ErrfatalPCI-X Detected Split Completion Master Abort Severity Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Type Reset DescriptionOffset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterOffset 170h SSR-Strap Status Register Offset 170h SSR-Strap Status RegisterReserved Read only SMBUS5 SMBUS3 SMBUS2 SMBUS16360 RsvdP Offset 178h PREFCTRL-Prefetch Control RegisterOffset 178h PREFCTRL-Prefetch Control Register Offset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data Register
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