Intel 41210 manual Offset 3Eh BCTRL-Bridge Control Sheet 1

Page 88

Register Description

12.2.20Offset 3Eh: BCTRL—Bridge Control

This register provides extensions to the Command Register (“Offset 04h: PCICMD—Command Register” on page 78) that are specific to a bridge. The Bridge Control Register provides many of the same controls for the secondary interface that are provided by the Command Register for the primary interface. Some bits affect operation of both interfaces of the bridge.

Table 54.

Offset 3Eh: BCTRL—Bridge Control (Sheet 1 of 2)

 

 

 

 

 

Bits

 

Type

Reset

Description

 

 

 

 

 

15:12

 

RO

0h

Reserved

 

 

 

 

 

 

 

 

 

Discard Timer SERR# Enable (DTSE): This bit controls the generation of

 

 

 

 

ERR_NONFATAL/ERR_FATAL messages on the primary interface in response to a timer

 

 

 

 

discard on the secondary interface.

 

 

 

 

0 = The 41210 does not generate ERR_NONFATAL/ERR_FATAL on a secondary timer

 

 

 

 

discard.

11

 

RW

0b

1 = When the appropriate mask bit in the advanced capability register is clear, the 41210

 

does generate ERR_NONFATAL/ERR_FATAL in response to a secondary timer

 

 

 

 

 

 

 

 

discard.

 

 

 

 

NOTE: ERR_NONFATAL/ERR_FATAL messages may also be generated when the

 

 

 

 

corresponding mask bit in the Uncorrectable Error Mask Register (“Offset 108h:

 

 

 

 

ERRUNC_MSK—PCI Express* Uncorrectable Error Mask” on page 106) is

 

 

 

 

cleared.

 

 

 

 

 

10

 

RWC

0b

Discard Timer Status (DTS): This bit is set to 1 when the secondary discard timer expires

 

(there is no discard timer for the primary interface).

 

 

 

 

 

 

 

 

 

 

 

 

 

Secondary Discard Timer (SDT): This bit sets the maximum number of PCI clock cycles

 

 

 

 

during which the bridge waits for an initiator on PCI to repeat a delayed transaction request.

 

 

 

 

The counter starts as soon as the delayed transaction completion is at the head of the

9

 

RW

0b

queue. When the master has not repeated the transaction at least once before the counter

 

expires, the bridge discards the transaction from its queues.

 

 

 

 

 

 

 

 

0 = The PCI master time-out value is between 215 and 216 PCI clocks.

 

 

 

 

1 = The PCI master time-out value is between 210 and 211 PCI clocks.

8

 

RW

0b

Primary Discard Timer (PDT): This bit is not relevant to PCI Express*.

 

 

 

 

 

7

 

RO

0b

Fast Back-to-Back Enable (FBE): The bridge cannot generate fast back-to-back cycles on

 

the PCI bus from PCI Express*-initiated transactions.

 

 

 

 

 

 

 

 

 

 

 

 

 

Secondary Bus Reset (SBR): This bit controls x_RST# assertion on PCI.

 

 

 

 

0 = The bridge does not force x_RST# assertion on the secondary interface.

 

 

 

 

1 = The bridge asserts PCIRST#. Bridge configuration registers are not reset when this bit

 

 

 

 

is set.

6

 

RW

0b

As soon as this bit is set, the bridge completes the currently running transaction on PCI and

 

 

 

 

then resets the bus. Note that it is the responsibility of the software to ensure that all

 

 

 

 

pending transactions with the bus segment are complete before setting this bit. When the

 

 

 

 

software fails to do this, transactions can be lost.

 

 

 

 

NOTE: Software must ensure the secondary bus x_RST# timing requirements when

 

 

 

 

clearing this bit.

 

 

 

 

 

88

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Page 87 Page 89
Image 88
Page 87 Page 89
Contents Intel 41210 Serial to Parallel PCI Bridge Developer’s ManualIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Revision History Date Revision DescriptionPCI-X Interface Features PCI Express* Interface FeaturesIntroduction1 SMBus Interface Power ManagementJtag Signal Description On-Die Termination ODTODT Signals AACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74ADEVSEL# BDEVSEL# AFRAME# BFRAME# AGNT#50 BGNT#50PCI Express* Interface Pins PCI Express* InterfacePERCOMP10 TotalPCI Interface Pins Sheet 1 PCI Bus Interface Two InstancesADEVSEL# AIRDY#PCI Interface Pins Sheet 2 PCI Clock and Reset Pins PCI Interface Pins 64-Bit ExtensionsPCI Bus Interface 64-Bit Extension Two Interfaces Interrupt Interface Pins Interrupt Interface Two InterfacesAINTA# AINTB# AINTC# AINTD#Reset Strap Pins Reset StrapsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsVoltage Pins Number DescriptionThis page Intentionally Left Blank PCI Mode Pin/Strap Encoding PCI-X InterfaceInitialization PCI-X Initialization PatternPCI Mode Transactions SupportedPCI Transactions Supported Transaction Encoding1Read Transactions PCI-X ModePCI-X Transactions Supported Configuration Transactions DelayedEnd Point Source Lock CyclesPCI Decoding Transaction TerminationPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface PCI-X Protocol Specifics Attributes2 4 GB and 4 K Page Crossover Wait StatesArbitration Split TransactionsFields Split Completion Abort RegistersInternal Arbitration Scheme BridgeM0 High Priority Group Lpg Low Priority B3173-01Power Management Hardware-Controlled Active State Power ManagementSoftware-Driven PCI-PM 1.1-Compatible Power Management PCI Bus Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank Addressable Space Access PCI-to-PCI Bridge a Configuration SpacePCI-to-PCI Bridge B Configuration Space Addressing5Configuration-Space Access PCI Express* Configuration AccessDevice Number Signal Used for Public/Private Secondary PCI DevicesAddressing Type 0 Configuration Access from PCI-X Interface Type 1 to Type 0 Translation PCI and PCI-XI/O Space Access Mechanism SMBus Configuration AccessO Forwarding Memory Space Access Mechanism Memory-Mapped I/O Window Memory ForwardingPrefetchable Memory Window VGA AddressingOpaque Memory Window § § Transaction Ordering Upstream Transaction OrderingUpstream Transaction Ordering Row Pass ColumnRelaxed Ordering/No-Snoop Support Downstream Transaction OrderingDownstream Transaction Ordering Legacy Interrupt Sharing Interrupt SupportINTx Routing Table Interrupt Routing for Devices behind a Bridge Interrupt Binding for Devices behind a BridgeDevice Number on Secondary BusSMBus Address Assignments System Management Bus InterfaceBit Value SMBus Commands SMBus Command EncodingInternal Command SMBus commandInitialization Sequence ConfigurationSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clock and Reset Device ResetClocking Clock DomainsRSTIN# Reset Mechanism PERST# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank PCI Express* Errors Error HandlingPCI Errors Error Types Termination of Completion Required TransactionsCompletion-Status Translation for Immediate Terminations PCI-X Termination PCI Express* CompletionIndex PCI-X Split Termination Message PCI ExpressSuccessful 00h Split Termination on PCI Express* Interface PCI Express* Completion Status PCI CompletionRegister Nomenclature and Access Attributes PERST# resetRegister Description Bit Attribute DefinitionsConfiguration Registers PCI/PCI-X Compatible Configuration region Capptr0xFFF 0x300 0x100 0x40 0x00 B3174-02Legacy Configuration Space Register PCI Express* Extended Configuration SpaceByte Offset Offset 04h PCICMD-Command Register Offset 04h PCICMD-Command Register Sheet 1Reset Description Offset 00h ID-IdentifiersOffset 04h PCICMD-Command Register Sheet 2 Offset 06h PSTS-Primary Device StatusOffset 06h PSTS-Primary Device Status Sheet 1 TypeOffset 08h REVID-Revision ID Offset 06h PSTS-Primary Device Status Sheet 2Offset 08h REVID-Revision ID BitsOffset 0Dh PMLT-Primary Master Latency Timer Offset 09h CC-Class CodeOffset 0Ch CLS-Cache-Line Size Offset 0Eh HEADTYP-Header TypeOffset 1Bh SMLT-Secondary Master Latency Timer Offset 1Bh SMLT-Secondary Master Latency TimerOffset 18h BNUM-Bus Numbers Offset 18h BNUM-Bus NumbersOffset 1Ch IOBL-I/O Base and Limit Offset 1Ch IOBL-I/O Base and LimitFFFh Support for 16-bit I/O addressing onlyOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary StatusOffset 20h MBL-Memory Base and Limit Offset 20h MBL-Memory Base and Limit3120 000h Must be less than this valueBits Type Reset Description Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 Bits Offset 30h IOBLU16-I/O Base and Limit Upper 16 BitsOffset 34h CAPP-Capabilities List Pointer Offset 3Ch INTR-Interrupt InformationOffset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 1Offset 3Eh BCTRL-Bridge Control Sheet 2 Offset 40h BCNF-Bridge Configuration Register Offset 40h BCNF-Bridge Configuration RegisterPeer Memory Read Enable Pmre Bit Maximum Number of Upstream Delayed TransactionsOffset 42h MTT-Multi-Transaction Timer Offset 43h PCLKC-PCI Clock ControlOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 45h EXPNXTP-Next Item PointerOffset 46h EXPCAP-PCI Express* Capability Default DescriptionOffset 46h EXPCAP-PCI Express* Capability Bit MaxReadRequestSize Offset 4Ch EXPDCTL-PCI Express* Device Control RegisterBit MaxPayloadSize Offset 50h EXPLCAP-PCI Express* Link Capabilities Register Offset 4Eh EXPDSTS-PCI Express* Device Status RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register Bits Type Default Description Offset 54h EXPLCTL-PCI Express* Link Control RegisterOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit LatencyOffset 5Ch MSICAPID-PCI Express* MSI Capability Identifier Offset 56h EXPLSTS-PCI Express* Link Status RegisterOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 6Ch PMCAPID-Power Management Capabilities Identifier Offset 5Eh MSIMC-PCI Express* MSI Message ControlOffset 60h MSIMA-PCI Express* MSI Message Address Offset 68h MSIMD-PCI Express* MSI Message DataOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management CapabilitiesOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management CapabilitiesOffset 72h PMBSE-Power Management Bridge Support Extensions Offset 70h PMPMCSR-Power Management Control/Status RegisterOffset 73h PMDATA-Power Management Data Field Offset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item PointerOffset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item PointerOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterPower Budgeting Capability as the next capability Advanced Error Reporting Extended Capability Version NumberID, indicating Advanced Error Reporting Capability When the configuration unit signals a completer abortOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskUnsupported Request Error Status Severity Flow Control Protocol Error Status SeverityData Link Protocol Error Severity Training Error Severity Not supportedOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error MaskOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Sheet 2 Logs the headerInternal Bridge Data Error Mask PCI Delayed Transaction Timer Expiry MaskPCI-X Uncorrectable Address Parity Error Detected Mask PCI-X Uncorrectable Attribute Parity Error Detected MaskPCI-X Detected Target Abort Mask optional in specification PCI-X Detected Split Completion Master Abort MaskInternal Bridge Data Error Severity PCI Delayed Transaction Timer Expiry SeverityPCI-X Uncorrectable Address Parity Error Detected Severity PCI-X Uncorrectable Data Parity Error Detected SeverityPCI-X Detected Split Completion Master Abort Severity Rwcs = Errnonfatal = ErrfatalRegister is cleared by the software writing a 1 to the bit Type Reset Description Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterOffset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterOffset 170h SSR-Strap Status Register Offset 170h SSR-Strap Status RegisterReserved Read only SMBUS5 SMBUS3 SMBUS2 SMBUS1Offset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data RegisterOffset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data Register
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