Intel 41210 manual 118

Contents
50	Offset 2Ch: PMLU32—Prefetchable Memory Limit Upper 32 Bits	87
51	Offset 30h: IOBLU16—I/O Base and Limit Upper 16 Bits	87
52	Offset 34h: CAPP—Capabilities List Pointer	87
53	Offset 3Ch: INTR—Interrupt Information	87
54	Offset 3Eh: BCTRL—Bridge Control	88
55	Offset 40h: BCNF—Bridge Configuration Register	90
56	Offset 42h: MTT—Multi-Transaction Timer	91
57	Offset 43h: PCLKC—PCI Clock Control	91
58	Offset 44h: PCI Express*_CAPID—PCI Express* Capability Identifier	91
59	Offset 45h: PCI Express*_NXTP—Next Item Pointer	91
60	Offset 46h: EXP_CAP—PCI Express* Capability	92
61	Offset 48h: EXP_DCAP—PCI Express* Device Capabilities Register	92
62	Offset 4Ch: EXP_DCTL—PCI Express* Device Control Register	93
63	Offset 4Eh: EXP_DSTS—PCI Express* Device Status Register	94
64	Offset 50h: EXP_LCAP—PCI Express* Link Capabilities Register	94
65	Offset 54h: EXP_LCTL—PCI Express* Link Control Register	95
66	Offset 56h: EXP_LSTS—PCI Express* Link Status Register	96
67	Offset 5Ch: MSI_CAPID—PCI Express* MSI Capability Identifier	96
68	Offset 5Dh: MSI_NXTP—PCI Express* Next Item Pointer	96
69	Offset 5Eh: MSI_MC—PCI Express* MSI Message Control	97
70	Offset 60h: MSI_MA—PCI Express* MSI Message Address	97
71	Offset 68h: MSI_MD—PCI Express* MSI Message Data	97
72	Offset 6Ch: PM_CAPID—Power Management Capabilities Identifier	97
73	Offset 6Dh: PM_NXTP—Power Management Next Item Pointer	98
74	Offset 6Eh: PM_PMC—Power Management Capabilities	98
75	Offset 70h: PM_PMCSR—Power Management Control/Status Register	99
76	Offset 72h: PM_BSE—Power Management Bridge Support Extensions	99
77	Offset 73h: PM_DATA—Power Management Data Field	99
78	Offset D8h: PX_CAPID—PCI-X Capabilities Identifier	100
79	Offset D9h: PX_NXTP—PCI-X Next Item Pointer	100
80	Offset DAh: PX_SSTS—PCI-X Secondary Status	101
81	Offset DCh: PX_BSTS—PCI-X Bridge Status	102
82	Offset E0h: PX_USTC—PCI-X Upstream Split Transaction Control	102
83	Offset E4h: PX_DSTC—PCI-X Downstream Split Transaction Control	103
84	Offset FCh: BINIT—Bridge Initialization Register	104
85	Offset 100h: EXPAERR_CAPID—PCI Express* Advanced Error Capability Identifier	105
86	Offset 104h: ERRUNC_STS—PCI Express* Uncorrectable Error Status Register	105
87	Offset 108h: ERRUNC_MSK—PCI Express* Uncorrectable Error Mask	106
88	Offset 10Ch: ERRUNC_SEV—PCI Express* Uncorrectable Error Severity	107
89	Offset 110h: ERRCOR_STS—PCI Express* Correctable Error Status	108
90	Offset 114h: ERRCOR_MSK—PCI Express* Correctable Error Mask	109
91	Offset 118h: ADVERR_CTL—Advanced Error Control and Capability Register	109
92	Offset 11C–12Bh:HDR_LOG—PCI Express* Transaction Header Log	110
93	Offset 12Ch: PCIXERRUNC_STS—UncorrectablePCI-X Status Register	111
94	Offset 130h: PCIXERRUNC_MSK—UncorrectablePCI-X Error Mask Register	113
95	Offset 130h: PCIXERRUNC_SEV—UncorrectablePCI-X Error Severity Register	115
96	Offset 138h: PCIXERRUNC_PTR—UncorrectablePCI-X Error Pointer Register	116
97	Offset 13C–14Bh:PCIXHDR_LOG—UncorrectablePCI-X Header Log	117
98	Offset 16Ah: ARB_CNTRL—Internal Arbiter Control Register	117
99	Offset 170h: SSR—Strap Status Register	118

8 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual