Addressing
5.5Memory Space Access Mechanism
The 41210 supports 64 bits of memory addressing on both interfaces.
Two memory windows can be setup for forwarding memory transactions from PCI
•
•Prefetchable memory base and limit (PMBL) registers
•Prefetchable memory base and limit upper 32 bits (PMBLU32) register
•Memory enable (MSE) bit in the command register
•Master enable bit (BME) in the command register
To enable downstream memory transactions, the memory space enable bit in the command register must be set (bit[1] of offset
Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual | 47 |