Intel 41210 manual Offset 1Eh SSTS-Secondary Status

Page 84

Register Description

12.2.12Offset 1Eh: SSTS—Secondary Status

For the writable bits in this register, writing 1 to the bit clears the bit. Writing 0 to the bit has no effect.

Table 46.

Offset 1Eh: SSTS—Secondary Status

 

 

 

 

 

Bits

 

Type

Reset

Description

 

 

 

 

 

 

 

 

 

Detected Parity Error (DPE): This bit is set to 1 whenever the bridge detects an address or

15

 

RWC

0b

data parity error on the PCI bus. This bit is set even when the Parity Error Response Enable

 

bit of the Bridge Control Register (bit[0], “Offset 3Eh: BCTRL—Bridge Control” on page 88)

 

 

 

 

 

 

 

 

is not set.

 

 

 

 

 

14

 

RWC

0b

Received System Error (RSE): This bit is set to 1 when a SERR# assertion is received

 

on PCI.

 

 

 

 

 

 

 

 

 

 

 

 

 

Received Master Abort (RMA): This bit is set to 1 whenever the bridge, as an initiator on

13

 

RWC

0b

the PCI bus, receives a master-abort, or when the bridge receives a PCI-X split completion

 

 

 

 

packet with a master-abort.

 

 

 

 

 

 

 

 

 

Received Target Abort (RTA): This bit is set to 1 whenever the bridge, as an initiator on

 

 

 

 

PCI, receives a target-abort on PCI. For “completion required” PCI Express* packets, this

12

 

RWC

0b

event forces a completion status of “target abort” on PCI Express*, and sets the Signaled

 

 

 

 

Target Abort in the Primary Status Register (“Offset 06h: PSTS—Primary Device Status” on

 

 

 

 

page 79).

 

 

 

 

 

11

 

RWC

0b

Signaled Target Abort (STA): This bit is set to 1 when the bridge, as a target on the PCI

 

bus, signals a target abort.

 

 

 

 

 

 

 

 

 

10:9

 

RO

01b

DEVSEL# Timing (DVT): These bits indicate that the 41210 responds in medium decode

 

time to transactions on the PCI interface (secondary bus).

 

 

 

 

 

 

 

 

 

 

 

 

 

Master Data Parity Error Detected (MDPD): This bit is set to 1 when all of the following

 

 

 

 

are true:

 

 

 

 

• The bridge is the initiator on PCI.

 

 

 

 

• PERR# is detected to be asserted.

8

 

RWC

0b

• The Parity Error Response Enable bit in the Bridge Control Register (bit[0], “Offset 3Eh:

 

 

 

 

BCTRL—Bridge Control” on page 88) is set.

 

 

 

 

This bit is also set when the 41210 receives a split-completion message from PCI-X, which

 

 

 

 

indicates a write data parity error (regardless of the setting of the Parity Error Response

 

 

 

 

Enable bit). Refer to PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b for

 

 

 

 

details.

 

 

 

 

 

7

 

RO

1b

Fast Back-to-Back Capable (FBC): This bit indicates that the secondary interface can

 

receive fast back-to-back cycles.

 

 

 

 

 

 

 

 

 

6

 

RO

0b

Reserved

 

 

 

 

 

5

 

RO

1b

66 MHz Capable (C66): This bit indicates that the secondary interface of the bridge is

 

66 MHz-capable.

 

 

 

 

 

 

 

 

 

4:0

 

RO

00h

Reserved

 

 

 

 

 

84

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Page 83 Page 85
Image 84
Page 83 Page 85
Contents Intel 41210 Serial to Parallel PCI Bridge Developer’s ManualIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Revision History Date Revision DescriptionPCI Express* Interface Features PCI-X Interface FeaturesIntroduction1 Power Management SMBus InterfaceJtag Signal Description On-Die Termination ODTODT Signals AACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74ADEVSEL# BDEVSEL# AFRAME# BFRAME# AGNT#50 BGNT#50PCI Express* Interface Pins PCI Express* InterfacePERCOMP10 TotalPCI Interface Pins Sheet 1 PCI Bus Interface Two InstancesADEVSEL# AIRDY#PCI Interface Pins Sheet 2 PCI Interface Pins 64-Bit Extensions PCI Clock and Reset PinsPCI Bus Interface 64-Bit Extension Two Interfaces Interrupt Interface Pins Interrupt Interface Two InterfacesAINTA# AINTB# AINTC# AINTD#Reset Straps Reset Strap PinsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsVoltage Pins Number DescriptionThis page Intentionally Left Blank PCI Mode Pin/Strap Encoding PCI-X InterfaceInitialization PCI-X Initialization PatternPCI Mode Transactions SupportedPCI Transactions Supported Transaction Encoding1PCI-X Mode Read TransactionsPCI-X Transactions Supported Configuration Transactions DelayedLock Cycles End Point SourcePCI Decoding Transaction TerminationPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface PCI-X Protocol Specifics Attributes2 4 GB and 4 K Page Crossover Wait StatesArbitration Split TransactionsFields Split Completion Abort RegistersInternal Arbitration Scheme BridgeM0 High Priority Group Lpg Low Priority B3173-01Power Management Hardware-Controlled Active State Power ManagementSoftware-Driven PCI-PM 1.1-Compatible Power Management PCI Bus Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank Addressable Space Access PCI-to-PCI Bridge a Configuration SpacePCI-to-PCI Bridge B Configuration Space Addressing5Configuration-Space Access PCI Express* Configuration AccessDevice Number Signal Used for Public/Private Secondary PCI DevicesAddressing Type 0 Configuration Access from PCI-X Interface Type 1 to Type 0 Translation PCI and PCI-XI/O Space Access Mechanism SMBus Configuration AccessO Forwarding Memory Space Access Mechanism Memory-Mapped I/O Window Memory ForwardingVGA Addressing Prefetchable Memory WindowOpaque Memory Window § § Transaction Ordering Upstream Transaction OrderingUpstream Transaction Ordering Row Pass ColumnDownstream Transaction Ordering Relaxed Ordering/No-Snoop SupportDownstream Transaction Ordering Interrupt Support Legacy Interrupt SharingINTx Routing Table Interrupt Routing for Devices behind a Bridge Interrupt Binding for Devices behind a BridgeDevice Number on Secondary BusSystem Management Bus Interface SMBus Address AssignmentsBit Value SMBus Commands SMBus Command EncodingInternal Command SMBus commandConfiguration Initialization SequenceSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clock and Reset Device ResetClocking Clock DomainsPERST# Reset Mechanism RSTIN# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank Error Handling PCI Express* ErrorsPCI Errors Error Types Termination of Completion Required TransactionsCompletion-Status Translation for Immediate Terminations PCI-X Termination PCI Express* CompletionPCI-X Split Termination Message PCI Express IndexSuccessful 00h Split Termination on PCI Express* Interface PCI Express* Completion Status PCI CompletionRegister Nomenclature and Access Attributes PERST# resetRegister Description Bit Attribute DefinitionsConfiguration Registers PCI/PCI-X Compatible Configuration region Capptr0xFFF 0x300 0x100 0x40 0x00 B3174-02Legacy Configuration Space PCI Express* Extended Configuration Space RegisterByte Offset Offset 04h PCICMD-Command Register Offset 04h PCICMD-Command Register Sheet 1Reset Description Offset 00h ID-IdentifiersOffset 04h PCICMD-Command Register Sheet 2 Offset 06h PSTS-Primary Device StatusOffset 06h PSTS-Primary Device Status Sheet 1 TypeOffset 08h REVID-Revision ID Offset 06h PSTS-Primary Device Status Sheet 2Offset 08h REVID-Revision ID BitsOffset 0Dh PMLT-Primary Master Latency Timer Offset 09h CC-Class CodeOffset 0Ch CLS-Cache-Line Size Offset 0Eh HEADTYP-Header TypeOffset 1Bh SMLT-Secondary Master Latency Timer Offset 1Bh SMLT-Secondary Master Latency TimerOffset 18h BNUM-Bus Numbers Offset 18h BNUM-Bus NumbersOffset 1Ch IOBL-I/O Base and Limit Offset 1Ch IOBL-I/O Base and LimitFFFh Support for 16-bit I/O addressing onlyOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary StatusOffset 20h MBL-Memory Base and Limit Offset 20h MBL-Memory Base and Limit3120 000h Must be less than this valueBits Type Reset Description Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 Bits Offset 30h IOBLU16-I/O Base and Limit Upper 16 BitsOffset 34h CAPP-Capabilities List Pointer Offset 3Ch INTR-Interrupt InformationOffset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 1Offset 3Eh BCTRL-Bridge Control Sheet 2 Offset 40h BCNF-Bridge Configuration Register Offset 40h BCNF-Bridge Configuration RegisterPeer Memory Read Enable Pmre Bit Maximum Number of Upstream Delayed TransactionsOffset 42h MTT-Multi-Transaction Timer Offset 43h PCLKC-PCI Clock ControlOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 45h EXPNXTP-Next Item PointerDefault Description Offset 46h EXPCAP-PCI Express* CapabilityOffset 46h EXPCAP-PCI Express* Capability Offset 4Ch EXPDCTL-PCI Express* Device Control Register Bit MaxReadRequestSizeBit MaxPayloadSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 50h EXPLCAP-PCI Express* Link Capabilities RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register Bits Type Default Description Offset 54h EXPLCTL-PCI Express* Link Control RegisterOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit LatencyOffset 56h EXPLSTS-PCI Express* Link Status Register Offset 5Ch MSICAPID-PCI Express* MSI Capability IdentifierOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 6Ch PMCAPID-Power Management Capabilities Identifier Offset 5Eh MSIMC-PCI Express* MSI Message ControlOffset 60h MSIMA-PCI Express* MSI Message Address Offset 68h MSIMD-PCI Express* MSI Message DataOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management CapabilitiesOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management CapabilitiesOffset 70h PMPMCSR-Power Management Control/Status Register Offset 72h PMBSE-Power Management Bridge Support ExtensionsOffset 73h PMDATA-Power Management Data Field Offset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item PointerOffset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item PointerOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterPower Budgeting Capability as the next capability Advanced Error Reporting Extended Capability Version NumberID, indicating Advanced Error Reporting Capability When the configuration unit signals a completer abortOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskUnsupported Request Error Status Severity Flow Control Protocol Error Status SeverityData Link Protocol Error Severity Training Error Severity Not supportedOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error MaskOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Sheet 2 Logs the headerInternal Bridge Data Error Mask PCI Delayed Transaction Timer Expiry MaskPCI-X Uncorrectable Address Parity Error Detected Mask PCI-X Uncorrectable Attribute Parity Error Detected MaskPCI-X Detected Target Abort Mask optional in specification PCI-X Detected Split Completion Master Abort MaskInternal Bridge Data Error Severity PCI Delayed Transaction Timer Expiry SeverityPCI-X Uncorrectable Address Parity Error Detected Severity PCI-X Uncorrectable Data Parity Error Detected SeverityRwcs = Errnonfatal = Errfatal PCI-X Detected Split Completion Master Abort SeverityRegister is cleared by the software writing a 1 to the bit Type Reset Description Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterOffset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterOffset 170h SSR-Strap Status Register Offset 170h SSR-Strap Status RegisterReserved Read only SMBUS5 SMBUS3 SMBUS2 SMBUS1Offset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data RegisterOffset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data Register
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