Intel 41210 manual Offset 42h MTT-Multi-Transaction Timer, Offset 43h PCLKC-PCI Clock Control

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Register Description

12.2.22Offset 42h: MTT—Multi-Transaction Timer

This register controls the amount of time that the 41210 arbiter allows for a PCI initiator to perform multiple back-to-back transactions on the PCI bus. The number of clocks programmed in the MTT represents the time slice (measured in PCI clocks) to be allotted to the current agent, after which the arbiter grants the bus to another agent that is requesting it.

Table 56.		Offset 42h: MTT—Multi-Transaction Timer

Bits		Type	Reset	Description

7:3		RW	00h	Timer Count Value (MTC): This field specifies the amount of time that the grant remains
7:3		RW	00h	asserted to a master that is continuously asserting its request for multiple transfers. This
				field specifies the count in an 8-clock (PCI clock) granularity.

2:0		RsvdP	000b	Preserved

12.2.23Offset 43h: PCLKC—PCI Clock Control

This register controls the enable and disable of the 41210 PCI clock outputs.

Table 57.		Offset 43h: PCLKC—PCI Clock Control

Bits		Type	Reset	Description

7		RsvdP	1b	Reserved

				PCI Feedback Clock Control:
6		RW	1b	0 = PCI feedback clock output buffer, X_CLK[6], is tristated.
				1 = PCI feedback clock output buffer, X_CLK[6], is enabled.

				PCI Clock Control: These bits enable the PCI clock output buffers, when all 1s. Otherwise
5:0		RW	1 1111b	the buffers are tristated. Bit[0] corresponds to X_CLKO[0], bit[1] corresponds to X_CLKO[1],
5:0		RW	1 1111b	etc.
				etc.
				The tristating of the clock is asynchronous to the output clocks.

12.2.24Offset 44h: EXP_CAPID—PCI Express* Capability Identifier

This register stores the PCI Express* capability ID value.

Table 58. Offset 44h: PCI Express*_CAPID—PCI Express* Capability Identifier

	Bits	Type	Reset	Description

	7:0	RO	10h	PCI Express* Capability ID: These bits indicate that the Intel® 41210 Serial to Parallel PCI
	7:0	RO	10h	Bridge has PCI Express* capability.
				Bridge has PCI Express* capability.

12.2.25Offset 45h: EXP_NXTP—Next Item Pointer

This register stores the byte offset pointer to the next capability list item of the bridge.

Table 59.		Offset 45h: PCI Express*_NXTP—Next Item Pointer

Bits		Type	Reset	Description

7:0		RO	5Ch	Next Capability Pointer: This field indicates the offset of the next capabilities list item,
7:0		RO	5Ch	which is the MSI capability.
				which is the MSI capability.

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

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Contents Developer’s Manual Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Date Revision Description Revision HistoryPCI-X Interface Features PCI Express* Interface FeaturesIntroduction1 SMBus Interface Power ManagementJtag On-Die Termination ODT Signal DescriptionAGNT#50 BGNT#50 ODT SignalsAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 ADEVSEL# BDEVSEL# AFRAME# BFRAME#Total PCI Express* Interface PinsPCI Express* Interface PERCOMP10AIRDY# PCI Interface Pins Sheet 1PCI Bus Interface Two Instances ADEVSEL#PCI Interface Pins Sheet 2 PCI Clock and Reset Pins PCI Interface Pins 64-Bit ExtensionsPCI Bus Interface 64-Bit Extension Two Interfaces AINTC# AINTD# Interrupt Interface PinsInterrupt Interface Two Interfaces AINTA# AINTB#Reset Strap Pins Reset StrapsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsNumber Description Voltage PinsThis page Intentionally Left Blank PCI-X Initialization Pattern PCI Mode Pin/Strap EncodingPCI-X Interface InitializationTransaction Encoding1 PCI ModeTransactions Supported PCI Transactions SupportedRead Transactions PCI-X ModePCI-X Transactions Supported Delayed Configuration TransactionsEnd Point Source Lock CyclesPCI Transaction Termination DecodingPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface Wait States PCI-X Protocol SpecificsAttributes 2 4 GB and 4 K Page CrossoverSplit Completion Abort Registers ArbitrationSplit Transactions FieldsBridgeM0 High Priority Group Lpg Low Priority B3173-01 Internal Arbitration SchemePCI Bus Power Management Power ManagementHardware-Controlled Active State Power Management Software-Driven PCI-PM 1.1-Compatible Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank Addressing5 Addressable Space AccessPCI-to-PCI Bridge a Configuration Space PCI-to-PCI Bridge B Configuration SpaceSecondary PCI Devices Configuration-Space AccessPCI Express* Configuration Access Device Number Signal Used for Public/PrivateAddressing Type 1 to Type 0 Translation PCI and PCI-X Type 0 Configuration Access from PCI-X InterfaceSMBus Configuration Access I/O Space Access MechanismO Forwarding Memory Space Access Mechanism Memory Forwarding Memory-Mapped I/O WindowPrefetchable Memory Window VGA AddressingOpaque Memory Window § § Row Pass Column Transaction OrderingUpstream Transaction Ordering Upstream Transaction OrderingRelaxed Ordering/No-Snoop Support Downstream Transaction OrderingDownstream Transaction Ordering Legacy Interrupt Sharing Interrupt SupportINTx Routing Table Secondary Bus Interrupt Routing for Devices behind a BridgeInterrupt Binding for Devices behind a Bridge Device Number onSMBus Address Assignments System Management Bus InterfaceBit Value SMBus command SMBus CommandsSMBus Command Encoding Internal CommandInitialization Sequence ConfigurationSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clock Domains Clock and ResetDevice Reset ClockingRSTIN# Reset Mechanism PERST# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank PCI Express* Errors Error HandlingPCI Errors PCI-X Termination PCI Express* Completion Error TypesTermination of Completion Required Transactions Completion-Status Translation for Immediate TerminationsIndex PCI-X Split Termination Message PCI ExpressSuccessful 00h PCI Express* Completion Status PCI Completion Split Termination on PCI Express* InterfaceBit Attribute Definitions Register Nomenclature and Access AttributesPERST# reset Register DescriptionConfiguration Registers B3174-02 PCI/PCI-X Compatible Configuration regionCapptr 0xFFF 0x300 0x100 0x40 0x00Legacy Configuration Space Register PCI Express* Extended Configuration SpaceByte Offset Offset 00h ID-Identifiers Offset 04h PCICMD-Command RegisterOffset 04h PCICMD-Command Register Sheet 1 Reset DescriptionType Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status Offset 06h PSTS-Primary Device Status Sheet 1Bits Offset 08h REVID-Revision IDOffset 06h PSTS-Primary Device Status Sheet 2 Offset 08h REVID-Revision IDOffset 0Eh HEADTYP-Header Type Offset 0Dh PMLT-Primary Master Latency TimerOffset 09h CC-Class Code Offset 0Ch CLS-Cache-Line SizeOffset 18h BNUM-Bus Numbers Offset 1Bh SMLT-Secondary Master Latency TimerOffset 1Bh SMLT-Secondary Master Latency Timer Offset 18h BNUM-Bus NumbersSupport for 16-bit I/O addressing only Offset 1Ch IOBL-I/O Base and LimitOffset 1Ch IOBL-I/O Base and Limit FFFhOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary StatusMust be less than this value Offset 20h MBL-Memory Base and LimitOffset 20h MBL-Memory Base and Limit 3120 000hOffset 24h PMBL-Prefetchable Memory Base and Limit Bits Type Reset DescriptionOffset 24h PMBL-Prefetchable Memory Base and Limit Offset 28h PMBU32-Prefetchable Memory Base Upper 32 BitsOffset 3Ch INTR-Interrupt Information Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 34h CAPP-Capabilities List PointerOffset 3Eh BCTRL-Bridge Control Sheet 1 Offset 3Eh BCTRL-Bridge ControlOffset 3Eh BCTRL-Bridge Control Sheet 2 Bit Maximum Number of Upstream Delayed Transactions Offset 40h BCNF-Bridge Configuration RegisterOffset 40h BCNF-Bridge Configuration Register Peer Memory Read Enable PmreOffset 45h EXPNXTP-Next Item Pointer Offset 42h MTT-Multi-Transaction TimerOffset 43h PCLKC-PCI Clock Control Offset 44h EXPCAPID-PCI Express* Capability IdentifierOffset 46h EXPCAP-PCI Express* Capability Default DescriptionOffset 46h EXPCAP-PCI Express* Capability Bit MaxReadRequestSize Offset 4Ch EXPDCTL-PCI Express* Device Control RegisterBit MaxPayloadSize Offset 50h EXPLCAP-PCI Express* Link Capabilities Register Offset 4Eh EXPDSTS-PCI Express* Device Status RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register L0s Exit Latency Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register Offset 54h EXPLCTL-PCI Express* Link Control RegisterOffset 5Ch MSICAPID-PCI Express* MSI Capability Identifier Offset 56h EXPLSTS-PCI Express* Link Status RegisterOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 68h MSIMD-PCI Express* MSI Message Data Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 5Eh MSIMC-PCI Express* MSI Message Control Offset 60h MSIMA-PCI Express* MSI Message AddressOffset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 72h PMBSE-Power Management Bridge Support Extensions Offset 70h PMPMCSR-Power Management Control/Status RegisterOffset 73h PMDATA-Power Management Data Field Offset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterWhen the configuration unit signals a completer abort Power Budgeting Capability as the next capabilityAdvanced Error Reporting Extended Capability Version Number ID, indicating Advanced Error Reporting CapabilityOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskTraining Error Severity Not supported Unsupported Request Error Status SeverityFlow Control Protocol Error Status Severity Data Link Protocol Error SeverityOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error MaskOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Logs the header Sheet 2PCI-X Uncorrectable Attribute Parity Error Detected Mask Internal Bridge Data Error MaskPCI Delayed Transaction Timer Expiry Mask PCI-X Uncorrectable Address Parity Error Detected MaskPCI-X Detected Split Completion Master Abort Mask PCI-X Detected Target Abort Mask optional in specificationPCI-X Uncorrectable Data Parity Error Detected Severity Internal Bridge Data Error SeverityPCI Delayed Transaction Timer Expiry Severity PCI-X Uncorrectable Address Parity Error Detected SeverityPCI-X Detected Split Completion Master Abort Severity Rwcs = Errnonfatal = ErrfatalRegister is cleared by the software writing a 1 to the bit Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Type Reset DescriptionOffset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header LogSMBUS5 SMBUS3 SMBUS2 SMBUS1 Offset 170h SSR-Strap Status RegisterOffset 170h SSR-Strap Status Register Reserved Read onlyOffset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register

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