Intel 41210 manual Sheet 1

Page 111

Register Description

12.2.59Offset 12Ch: PCIXERRUNC_STS—Uncorrectable PCI-X Status Register

Table 93.

Offset 12Ch: PCIXERRUNC_STS—Uncorrectable PCI-X Status Register

 

 

(Sheet 1 of 2)

 

 

 

 

 

 

Bits

 

Type

Reset

Description

 

 

 

 

 

15:14

 

RsvdZ

00b

Reserved Zero: Software must write 0 to these bits.

 

 

 

 

 

 

 

 

 

Internal Bridge Data Error: This bit is set when an error occurs in the internal data queues

13

 

RWCS

0b

in the Intel® 41210 Serial to Parallel PCI Bridge in either direction. The 41210 does not log

 

 

 

 

any headers for this error.

 

 

 

 

 

12

 

RWCS

0b

PCI-X SERR# Detected: The 41210 sets this bit whenever it detects that the PCI SERR#

 

pin is asserted. There is no header logging associated with the setting of this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI-X PERR# Detected: The 41210 sets this bit whenever it detects that the PCI bus

 

 

 

 

PERR# pin is asserted when it is mastering a write (memory, I/O, or configuration) or

 

 

 

 

sourcing data during a split/delayed read completion on its secondary interface. The 41210

 

 

 

 

logs the header of the transaction in which the PERR# is detected (regardless of the data

 

 

 

 

phase in which it is detected) in the PCI-X header log register (“Offset 11C–12Bh:

 

 

 

 

HDR_LOG—PCI Express* Transaction Header Log” on page 110). This bit is also set when

11

 

RWCS

0b

the bridge receives a PCI-X Split Completion Message with write data parity error status.

 

 

 

 

The header log under this condition is the command, address, and attribute portion of the

 

 

 

 

Split Completion Message.

 

 

 

 

NOTE: This status bit and the associated header log are always updated regardless of

 

 

 

 

whether the PERR# detected was the result of a PCI bus error or of forwarded

 

 

 

 

poisoned data. However, error messages are not escalated to PCI Express* when

 

 

 

 

the PERR# detection is due to forwarded poisoned data.

 

 

 

 

 

 

 

 

 

PCI Delayed Transaction Timer Expiry: This bit is set by the 41210 when it detects that a

10

 

RWCS

0b

DT time-out has occurred on a delayed read stream or on an upstream I/O or configuration

 

 

 

 

transaction. No header is logged.

 

 

 

 

 

 

 

 

 

PCI-X Uncorrectable Address Parity Error Detected: The 41210 sets this bit when it is

 

 

 

 

the target of an upstream transaction and an address parity error is detected by the 41210

9

 

RWCS

0b

(regardless of whether the bus mode is PCI or PCI-X). The 41210 logs the header of the

 

 

 

 

transaction in which it detected the address/attribute parity error in the PCI-X header log

 

 

 

 

register.

 

 

 

 

 

 

 

 

 

PCI-X Uncorrectable Attribute Parity Error Detected: The 41210 sets this bit when it is

8

 

RWCS

0b

the target of an upstream transaction and an attribute parity error is detected by the 41210.

 

The 41210 logs the header of the transaction in which it detected the address/attribute

 

 

 

 

 

 

 

 

parity error in the PCI-X header log register.

 

 

 

 

 

 

 

 

 

PCI-X Uncorrectable Data Parity Error Detected: The 41210 sets this bit in all PCI modes

 

 

 

 

(PCI, PCI-X) when it is the target of a transaction or when it is mastering a PCI delayed read

7

 

RWCS

0b

with target sourcing data to the 41210, and a data parity error was detected by the 41210.

 

 

 

 

The 41210 logs the header of the transaction in which it detected the data parity error in the

 

 

 

 

PCI-X header log register.

 

 

 

 

 

6

 

RWCS

0b

Split Completion Message Data Error: This bit is set when a split completion message is

 

received with an uncorrectable data parity error.

 

 

 

 

 

 

 

 

 

 

 

 

 

Unexpected Split Completion: This bit is set when a completion is received from PCI-X

5

 

RWCS

0b

that matches the bus number range on the primary side of the 41210 but the Requester

 

ID:tag combination does not match one of the NP transmissions that the 41210 has

 

 

 

 

 

 

 

 

outstanding on PCI-X.

 

 

 

 

 

4

 

RsvdZ

0b

Reserved Zero: Software must write a 0 to this bit.

 

 

 

 

 

 

 

 

 

PCI-X Detected Master Abort: The 41210 sets this bit when it is the master of a request

3

 

RWCS

0b

transaction on the PCI-X bus and it receives a master abort. The 41210 logs the header for

 

that transaction. This bit is also set when the bridge receives a PCI-X Split Completion

 

 

 

 

Message with Master Abort Status. The header log under this condition is the command,

 

 

 

 

address, and attribute portion of the Split Completion Message.

 

 

 

 

 

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

111

Page 110 Page 112
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Page 110 Page 112
Contents Developer’s Manual Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Date Revision Description Revision HistoryPCI Express* Interface Features PCI-X Interface FeaturesIntroduction1 Power Management SMBus InterfaceJtag On-Die Termination ODT Signal DescriptionAGNT#50 BGNT#50 ODT SignalsAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 ADEVSEL# BDEVSEL# AFRAME# BFRAME#Total PCI Express* Interface PinsPCI Express* Interface PERCOMP10AIRDY# PCI Interface Pins Sheet 1PCI Bus Interface Two Instances ADEVSEL#PCI Interface Pins Sheet 2 PCI Interface Pins 64-Bit Extensions PCI Clock and Reset PinsPCI Bus Interface 64-Bit Extension Two Interfaces AINTC# AINTD# Interrupt Interface PinsInterrupt Interface Two Interfaces AINTA# AINTB#Reset Straps Reset Strap PinsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsNumber Description Voltage PinsThis page Intentionally Left Blank PCI-X Initialization Pattern PCI Mode Pin/Strap EncodingPCI-X Interface InitializationTransaction Encoding1 PCI ModeTransactions Supported PCI Transactions SupportedPCI-X Mode Read TransactionsPCI-X Transactions Supported Delayed Configuration TransactionsLock Cycles End Point SourcePCI Transaction Termination DecodingPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface Wait States PCI-X Protocol SpecificsAttributes 2 4 GB and 4 K Page CrossoverSplit Completion Abort Registers ArbitrationSplit Transactions FieldsBridgeM0 High Priority Group Lpg Low Priority B3173-01 Internal Arbitration SchemePCI Bus Power Management Power ManagementHardware-Controlled Active State Power Management Software-Driven PCI-PM 1.1-Compatible Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank Addressing5 Addressable Space AccessPCI-to-PCI Bridge a Configuration Space PCI-to-PCI Bridge B Configuration SpaceSecondary PCI Devices Configuration-Space AccessPCI Express* Configuration Access Device Number Signal Used for Public/PrivateAddressing Type 1 to Type 0 Translation PCI and PCI-X Type 0 Configuration Access from PCI-X InterfaceSMBus Configuration Access I/O Space Access MechanismO Forwarding Memory Space Access Mechanism Memory Forwarding Memory-Mapped I/O WindowVGA Addressing Prefetchable Memory WindowOpaque Memory Window § § Row Pass Column Transaction OrderingUpstream Transaction Ordering Upstream Transaction OrderingDownstream Transaction Ordering Relaxed Ordering/No-Snoop SupportDownstream Transaction Ordering Interrupt Support Legacy Interrupt SharingINTx Routing Table Secondary Bus Interrupt Routing for Devices behind a BridgeInterrupt Binding for Devices behind a Bridge Device Number onSystem Management Bus Interface SMBus Address AssignmentsBit Value SMBus command SMBus CommandsSMBus Command Encoding Internal CommandConfiguration Initialization SequenceSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clock Domains Clock and ResetDevice Reset ClockingPERST# Reset Mechanism RSTIN# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank Error Handling PCI Express* ErrorsPCI Errors PCI-X Termination PCI Express* Completion Error TypesTermination of Completion Required Transactions Completion-Status Translation for Immediate TerminationsPCI-X Split Termination Message PCI Express IndexSuccessful 00h PCI Express* Completion Status PCI Completion Split Termination on PCI Express* InterfaceBit Attribute Definitions Register Nomenclature and Access AttributesPERST# reset Register DescriptionConfiguration Registers B3174-02 PCI/PCI-X Compatible Configuration regionCapptr 0xFFF 0x300 0x100 0x40 0x00Legacy Configuration Space PCI Express* Extended Configuration Space RegisterByte Offset Offset 00h ID-Identifiers Offset 04h PCICMD-Command RegisterOffset 04h PCICMD-Command Register Sheet 1 Reset DescriptionType Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status Offset 06h PSTS-Primary Device Status Sheet 1Bits Offset 08h REVID-Revision IDOffset 06h PSTS-Primary Device Status Sheet 2 Offset 08h REVID-Revision IDOffset 0Eh HEADTYP-Header Type Offset 0Dh PMLT-Primary Master Latency TimerOffset 09h CC-Class Code Offset 0Ch CLS-Cache-Line SizeOffset 18h BNUM-Bus Numbers Offset 1Bh SMLT-Secondary Master Latency TimerOffset 1Bh SMLT-Secondary Master Latency Timer Offset 18h BNUM-Bus NumbersSupport for 16-bit I/O addressing only Offset 1Ch IOBL-I/O Base and LimitOffset 1Ch IOBL-I/O Base and Limit FFFhOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary StatusMust be less than this value Offset 20h MBL-Memory Base and LimitOffset 20h MBL-Memory Base and Limit 3120 000hOffset 24h PMBL-Prefetchable Memory Base and Limit Bits Type Reset DescriptionOffset 24h PMBL-Prefetchable Memory Base and Limit Offset 28h PMBU32-Prefetchable Memory Base Upper 32 BitsOffset 3Ch INTR-Interrupt Information Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 34h CAPP-Capabilities List PointerOffset 3Eh BCTRL-Bridge Control Sheet 1 Offset 3Eh BCTRL-Bridge ControlOffset 3Eh BCTRL-Bridge Control Sheet 2 Bit Maximum Number of Upstream Delayed Transactions Offset 40h BCNF-Bridge Configuration RegisterOffset 40h BCNF-Bridge Configuration Register Peer Memory Read Enable PmreOffset 45h EXPNXTP-Next Item Pointer Offset 42h MTT-Multi-Transaction TimerOffset 43h PCLKC-PCI Clock Control Offset 44h EXPCAPID-PCI Express* Capability IdentifierDefault Description Offset 46h EXPCAP-PCI Express* CapabilityOffset 46h EXPCAP-PCI Express* Capability Offset 4Ch EXPDCTL-PCI Express* Device Control Register Bit MaxReadRequestSizeBit MaxPayloadSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 50h EXPLCAP-PCI Express* Link Capabilities RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register L0s Exit Latency Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register Offset 54h EXPLCTL-PCI Express* Link Control RegisterOffset 56h EXPLSTS-PCI Express* Link Status Register Offset 5Ch MSICAPID-PCI Express* MSI Capability IdentifierOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 68h MSIMD-PCI Express* MSI Message Data Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 5Eh MSIMC-PCI Express* MSI Message Control Offset 60h MSIMA-PCI Express* MSI Message AddressOffset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 70h PMPMCSR-Power Management Control/Status Register Offset 72h PMBSE-Power Management Bridge Support ExtensionsOffset 73h PMDATA-Power Management Data Field Offset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterWhen the configuration unit signals a completer abort Power Budgeting Capability as the next capabilityAdvanced Error Reporting Extended Capability Version Number ID, indicating Advanced Error Reporting CapabilityOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskTraining Error Severity Not supported Unsupported Request Error Status SeverityFlow Control Protocol Error Status Severity Data Link Protocol Error SeverityOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error MaskOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Logs the header Sheet 2PCI-X Uncorrectable Attribute Parity Error Detected Mask Internal Bridge Data Error MaskPCI Delayed Transaction Timer Expiry Mask PCI-X Uncorrectable Address Parity Error Detected MaskPCI-X Detected Split Completion Master Abort Mask PCI-X Detected Target Abort Mask optional in specificationPCI-X Uncorrectable Data Parity Error Detected Severity Internal Bridge Data Error SeverityPCI Delayed Transaction Timer Expiry Severity PCI-X Uncorrectable Address Parity Error Detected SeverityRwcs = Errnonfatal = Errfatal PCI-X Detected Split Completion Master Abort SeverityRegister is cleared by the software writing a 1 to the bit Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Type Reset DescriptionOffset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header LogSMBUS5 SMBUS3 SMBUS2 SMBUS1 Offset 170h SSR-Strap Status RegisterOffset 170h SSR-Strap Status Register Reserved Read onlyOffset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register
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