Intel 41210 manual Error Handling

System Management Bus Interface

Figure 11. DWord Configuration Write Protocol (SMBus Byte Write, PEC Enabled)

S	11X0_XXX	W	A	Cmd = 10011000	A	Bus Number	A	PEC	A	P
S	11X0_XXX	W	A	Cmd = 00011000	A	Device/Function	A	PEC	A	P
S	11X0_XXX	W	A	Cmd = 00011000	A	Reg Number[15:8]	A	PEC	A	P
S	11X0_XXX	W	A	Cmd = 00011000	A	Reg Number[7:0]	A	PEC	A	P

S 11X0_XXX

W A

Cmd = 00011000

A

Data[W:X]

A

PEC

A P

S 11X0_XXX

W A

Cmd = 01011000

A

Data[Y:Z]

A

PEC

Clock Stretch

A P

B3192-01

8.3Error Handling

The SMBus slave interface handles two types of errors: internal and PEC.

Internal errors can occur when the target function is busy servicing a request from the PCI Express* interface. The SMBus unit may time-out these transactions and return a NACK for the read or write command. Additionally, an internal error can occur when the read or write command receives a master or target abort on the internal interface. When the master receives a NACK, the entire transaction must be reattempted.

When the master supports packet error checking (PEC), and the PEC enable bit in the command is set, the PEC byte is checked in the slave interface. When the check indicates a failure, the slave NACKs the PEC packet and does not issue the command on the internal interface.

Note: An SMBus master must either do PEC on all transactions in a sequence or not do it at all. PEC cannot be disabled in the middle of a sequence. A PEC error in the middle of a sequence must be re-started from the beginning of the sequence that set the begin bit.

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 61