Signal Description
2.8SMBus Interface
Table 8. | SMBus Interface Pins |
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Signal | I/O |
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| Description |
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SMBCLK | I/OD | SMBus Clock: This signal must be pulled to 3.3 V through an 8.2 KΩ | resistor. | ||
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SMBDAT | I/OD | SMBus Data: This signal must be pulled to 3.3 V through an 8.2 KΩ | resistor. | ||
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| SMBus Addressing Straps: These straps set the SMBus address for the 41210 Bridge. The address | |||
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| is determined as indicated below: |
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| • | Bit[7] | 1 |
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| • | Bit[6] | 1 |
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SMBUS[5] |
| • | Bit[5] | SMBUS[5] |
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I | • | Bit[4] | 0 |
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SMBUS[3:1] |
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| • | Bit[3] | SMBUS[3] |
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| • | Bit[2] | SMBUS[2] |
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| • | Bit[1] | SMBUS[1] |
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| These signals (bits[5], [3:1]) must be pulled up to 3.3 V or down to ground. Sampled at the rising edge | |||
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| of PERST#. |
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Total | 6 |
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Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual | 21 |