Intel 41210 manual 10.1

Contents
		5.3.1	PCI Express* Configuration Access	42
		5.3.2	Type 0 Configuration Access from PCI-X Interface	44
		5.3.3	SMBus Configuration Access	45
	5.4	I/O Space Access Mechanism		45
	5.5	Memory Space Access Mechanism		47
		5.5.1	Memory-Mapped I/O Window	48
		5.5.2	Prefetchable Memory Window	49
		5.5.3	Opaque Memory Window	49
	5.6	VGA Addressing		49
6	Transaction Ordering			51
	6.1	Upstream Transaction Ordering		51
	6.2	Downstream Transaction Ordering		52
	6.3	Relaxed Ordering/No-Snoop Support		52
7	Interrupt Support			53
	7.1	Legacy Interrupt Sharing		53
	7.2	Interrupt Routing for Devices behind a Bridge		54
8	System Management Bus Interface			55
	8.1	SMBus Commands		56
	8.2	Initialization Sequence		57
		8.2.1	Configuration	57
		8.2.2	Configuration Writes	60
	8.3	Error Handling		61
	8.4	SMBus Interface Reset		62
9	Local Initialization			63
10	Clock and Reset			65
	10.1	Clocking		65
	10.2	Device Reset		65
		10.2.1	PERST# Reset Mechanism	66
		10.2.2	RSTIN# Reset Mechanism	66
		10.2.3	PCI Express* Reset Mechanism	66
		10.2.4	Software PCI Reset (SBR—Secondary Bus Reset)	67
11	Error Handling			69
	11.1	PCI Express* Errors		69
	11.2	PCI Errors		69
		11.2.1	Error Types	70
		11.2.2	Termination of Completion Required Transactions	70
12	Register Description			73
	12.1	Register Nomenclature and Access Attributes		73
	12.2	Configuration Registers		74
		12.2.1	Offset 00h: ID—Identifiers	78
		12.2.2	Offset 04h: PCICMD—Command Register	78
		12.2.3	Offset 06h: PSTS—Primary Device Status	79
		12.2.4	Offset 08h: REVID—Revision ID	80
		12.2.5	Offset 09h: CC—Class Code	81

4 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual