Intel 41210 Offset 00h ID-Identifiers, Offset 04h PCICMD-Command Register, Reset Description

Page 78

Register Description

12.2.1Offset 00h: ID—Identifiers

 

 

Contains the vendor and device identifiers for software.

Table 35.

Offset 00h: ID—Identifiers

 

 

 

 

 

 

 

Bits

 

Type

 

Reset

Description

 

 

 

 

 

 

 

31:16

 

RO

A

 

B

Device ID (DID): These bits indicate the device number assigned by Intel to the Intel®

 

0340h

0341h

41210 Serial to Parallel PCI Bridge.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15:0

 

RO

 

8086h

Vendor ID (VID): This 16-bit field indicates that Intel is the vendor.

 

 

 

 

 

 

 

12.2.2Offset 04h: PCICMD—Command Register

This register controls how the device behaves on the primary interface (PCI Express*). As this component is a bridge, additional command information is located in a separate Bridge Control register (“Offset 3Eh: BCTRL—Bridge Control” on page 88).

Table 36.

Offset 04h: PCICMD—Command Register (Sheet 1 of 2)

 

 

 

 

 

Bits

 

Type

Reset

Description

 

 

 

 

 

15:11

 

RO

00h

Reserved

 

 

 

 

 

10

 

RW

0b

INTx Mask: The bridge does not generate internal interrupts. The value of this bit has no

 

meaning.

 

 

 

 

9

 

RO

0b

Fast Back-to-back enable (FBE): This bit has no meaning on PCI Express*.

 

This bit must be hard-wired to 0.

 

 

 

 

 

 

 

 

SERR# Enable (SEE): This bit enables reporting of non-fatal and fatal errors to the root

 

 

 

 

complex.

8

 

RW

0b

0 = Disable reporting errors

 

1 = Enable reporting of non-fatal and fatal errors to the root complex

 

 

 

 

NOTE: Errors are reported when enabled either through this bit or through the PCI

 

 

 

 

Express*-specific bits in the Device Control Register (“Offset 4Ch: EXP_DCTL—

 

 

 

 

PCI Express* Device Control Register” on page 93).

7

 

RO

0b

Wait Cycle Control (WCC): Reserved

 

 

 

 

 

 

 

 

 

Parity Error Response Enable (PERE): This bit controls the setting of the master data

 

 

 

 

parity error bit in the Status Register (“Offset 06h: PSTS—Primary Device Status” on

 

 

 

 

page 79) in response to a parity error received on the PCI Express* interface (poisoned

6

 

RW

0b

TLP) or peer PCI interface.

 

0 = The 41210 ignores these errors on the PCI Express*/peer-PCI interface.

 

 

 

 

 

 

 

 

1 = The 41210 reports read completion data parity errors on PCI Express* and sets the

 

 

 

 

MDPD bit in the status register.

 

 

 

 

 

5

 

RO

0b

VGA Palette Snoop Enable (VGA_PSE): Reserved

 

 

 

 

 

4

 

RO

0b

Memory Write and Invalidate Enable (MWIE): Memory write and invalidate transactions

 

are not generated, since PCI Express* does not have a corresponding transfer type.

 

 

 

 

3

 

RO

0b

Special Cycle Enable (SCE): Reserved

 

 

 

 

 

78

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Page 77 Page 79
Image 78
Page 77 Page 79
Contents Intel 41210 Serial to Parallel PCI Bridge Developer’s ManualIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Revision History Date Revision DescriptionPCI Express* Interface Features PCI-X Interface FeaturesIntroduction1 Power Management SMBus InterfaceJtag Signal Description On-Die Termination ODTADEVSEL# BDEVSEL# AFRAME# BFRAME# ODT SignalsAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 AGNT#50 BGNT#50PERCOMP10 PCI Express* Interface PinsPCI Express* Interface TotalADEVSEL# PCI Interface Pins Sheet 1PCI Bus Interface Two Instances AIRDY#PCI Interface Pins Sheet 2 PCI Interface Pins 64-Bit Extensions PCI Clock and Reset PinsPCI Bus Interface 64-Bit Extension Two Interfaces AINTA# AINTB# Interrupt Interface PinsInterrupt Interface Two Interfaces AINTC# AINTD#Reset Straps Reset Strap PinsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsVoltage Pins Number DescriptionThis page Intentionally Left Blank Initialization PCI Mode Pin/Strap EncodingPCI-X Interface PCI-X Initialization PatternPCI Transactions Supported PCI ModeTransactions Supported Transaction Encoding1PCI-X Mode Read TransactionsPCI-X Transactions Supported Configuration Transactions DelayedLock Cycles End Point SourcePCI Decoding Transaction TerminationPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface 2 4 GB and 4 K Page Crossover PCI-X Protocol SpecificsAttributes Wait StatesFields ArbitrationSplit Transactions Split Completion Abort RegistersInternal Arbitration Scheme BridgeM0 High Priority Group Lpg Low Priority B3173-01Software-Driven PCI-PM 1.1-Compatible Power Management Power ManagementHardware-Controlled Active State Power Management PCI Bus Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank PCI-to-PCI Bridge B Configuration Space Addressable Space AccessPCI-to-PCI Bridge a Configuration Space Addressing5Device Number Signal Used for Public/Private Configuration-Space AccessPCI Express* Configuration Access Secondary PCI DevicesAddressing Type 0 Configuration Access from PCI-X Interface Type 1 to Type 0 Translation PCI and PCI-XI/O Space Access Mechanism SMBus Configuration AccessO Forwarding Memory Space Access Mechanism Memory-Mapped I/O Window Memory ForwardingVGA Addressing Prefetchable Memory WindowOpaque Memory Window § § Upstream Transaction Ordering Transaction OrderingUpstream Transaction Ordering Row Pass ColumnDownstream Transaction Ordering Relaxed Ordering/No-Snoop SupportDownstream Transaction Ordering Interrupt Support Legacy Interrupt SharingINTx Routing Table Device Number on Interrupt Routing for Devices behind a BridgeInterrupt Binding for Devices behind a Bridge Secondary BusSystem Management Bus Interface SMBus Address AssignmentsBit Value Internal Command SMBus CommandsSMBus Command Encoding SMBus commandConfiguration Initialization SequenceSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clocking Clock and ResetDevice Reset Clock DomainsPERST# Reset Mechanism RSTIN# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank Error Handling PCI Express* ErrorsPCI Errors Completion-Status Translation for Immediate Terminations Error TypesTermination of Completion Required Transactions PCI-X Termination PCI Express* CompletionPCI-X Split Termination Message PCI Express IndexSuccessful 00h Split Termination on PCI Express* Interface PCI Express* Completion Status PCI CompletionRegister Description Register Nomenclature and Access AttributesPERST# reset Bit Attribute DefinitionsConfiguration Registers 0xFFF 0x300 0x100 0x40 0x00 PCI/PCI-X Compatible Configuration regionCapptr B3174-02Legacy Configuration Space PCI Express* Extended Configuration Space RegisterByte Offset Reset Description Offset 04h PCICMD-Command RegisterOffset 04h PCICMD-Command Register Sheet 1 Offset 00h ID-IdentifiersOffset 06h PSTS-Primary Device Status Sheet 1 Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status TypeOffset 08h REVID-Revision ID Offset 08h REVID-Revision IDOffset 06h PSTS-Primary Device Status Sheet 2 BitsOffset 0Ch CLS-Cache-Line Size Offset 0Dh PMLT-Primary Master Latency TimerOffset 09h CC-Class Code Offset 0Eh HEADTYP-Header TypeOffset 18h BNUM-Bus Numbers Offset 1Bh SMLT-Secondary Master Latency TimerOffset 1Bh SMLT-Secondary Master Latency Timer Offset 18h BNUM-Bus NumbersFFFh Offset 1Ch IOBL-I/O Base and LimitOffset 1Ch IOBL-I/O Base and Limit Support for 16-bit I/O addressing onlyOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary Status3120 000h Offset 20h MBL-Memory Base and LimitOffset 20h MBL-Memory Base and Limit Must be less than this valueOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Bits Type Reset DescriptionOffset 24h PMBL-Prefetchable Memory Base and Limit Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 34h CAPP-Capabilities List Pointer Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 3Ch INTR-Interrupt InformationOffset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 1Offset 3Eh BCTRL-Bridge Control Sheet 2 Peer Memory Read Enable Pmre Offset 40h BCNF-Bridge Configuration RegisterOffset 40h BCNF-Bridge Configuration Register Bit Maximum Number of Upstream Delayed TransactionsOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 42h MTT-Multi-Transaction TimerOffset 43h PCLKC-PCI Clock Control Offset 45h EXPNXTP-Next Item PointerDefault Description Offset 46h EXPCAP-PCI Express* CapabilityOffset 46h EXPCAP-PCI Express* Capability Offset 4Ch EXPDCTL-PCI Express* Device Control Register Bit MaxReadRequestSizeBit MaxPayloadSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 50h EXPLCAP-PCI Express* Link Capabilities RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 54h EXPLCTL-PCI Express* Link Control Register Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit LatencyOffset 56h EXPLSTS-PCI Express* Link Status Register Offset 5Ch MSICAPID-PCI Express* MSI Capability IdentifierOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 60h MSIMA-PCI Express* MSI Message Address Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 5Eh MSIMC-PCI Express* MSI Message Control Offset 68h MSIMD-PCI Express* MSI Message DataOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Eh PMPMC-Power Management Capabilities Offset 6Eh PMPMC-Power Management CapabilitiesOffset 70h PMPMCSR-Power Management Control/Status Register Offset 72h PMBSE-Power Management Bridge Support ExtensionsOffset 73h PMDATA-Power Management Data Field Offset D8h PXCAPID-PCI-X Capabilities Identifier Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D9h PXNXTP-PCI-X Next Item Pointer Offset D9h PXNXTP-PCI-X Next Item PointerOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset DCh PXBSTS-PCI-X Bridge Status Offset DCh PXBSTS-PCI-X Bridge StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterID, indicating Advanced Error Reporting Capability Power Budgeting Capability as the next capabilityAdvanced Error Reporting Extended Capability Version Number When the configuration unit signals a completer abortOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskData Link Protocol Error Severity Unsupported Request Error Status SeverityFlow Control Protocol Error Status Severity Training Error Severity Not supportedOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error MaskOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Sheet 2 Logs the headerPCI-X Uncorrectable Address Parity Error Detected Mask Internal Bridge Data Error MaskPCI Delayed Transaction Timer Expiry Mask PCI-X Uncorrectable Attribute Parity Error Detected MaskPCI-X Detected Target Abort Mask optional in specification PCI-X Detected Split Completion Master Abort MaskPCI-X Uncorrectable Address Parity Error Detected Severity Internal Bridge Data Error SeverityPCI Delayed Transaction Timer Expiry Severity PCI-X Uncorrectable Data Parity Error Detected SeverityRwcs = Errnonfatal = Errfatal PCI-X Detected Split Completion Master Abort SeverityRegister is cleared by the software writing a 1 to the bit Offset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Type Reset DescriptionOffset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterReserved Read only Offset 170h SSR-Strap Status RegisterOffset 170h SSR-Strap Status Register SMBUS5 SMBUS3 SMBUS2 SMBUS1Offset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 308h PWRBGTDATA-Power Budgeting Data Register Offset 308h PWRBGTDATA-Power Budgeting Data Register
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