Intel 41210 manual Miscellaneous Pins

Page 22

Signal Description

2.9Miscellaneous Pins

Table 9.

Miscellaneous Pins

 

 

 

 

 

 

 

 

 

 

Signal

 

I/O

 

Description

 

 

 

 

 

 

 

 

 

 

 

Configuration Reset: This signal is asserted low when ever the bridge goes

 

 

 

 

 

through a fundemental reset (PERST#, RSTIN#, or PCI Express Reset). This

 

CFGRST#

 

O

 

signal should be used to indicate when the local initialization methods should be

 

 

 

executed.

 

 

 

 

 

 

 

 

 

 

Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more

 

 

 

 

 

information.

 

 

 

 

 

 

 

PERST#

 

I

 

PCI Express Fundamental Reset: When low, asynchronously resets the

 

 

 

internal logic (including sticky bits).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset In: When Asserted, this signal asynchronously resets the internal logic

 

RSTIN#

 

I

 

and asserts X_RST# output for both PCI interfaces. This signal should be pulled

 

 

 

 

 

high for adapter card usage.

 

 

 

 

 

 

 

 

 

 

 

TAP Clock In: This is the input clock to the JTAG TAP controller. Acceptable

 

TCK

 

I

 

frequency is 0-16MHz

 

 

 

 

 

If not utilizing JTAG, this signal can be left as a no connect.

 

 

 

 

 

 

 

 

 

 

 

Test Data In: This is the serial data input to the JTAG BSCAN shift register

 

TDI

 

I

 

chain and to the JTAG BSCAN control logic. This is latched in on the rising edge

 

 

 

of TCK.

 

 

 

 

 

 

 

 

 

 

If not utilizing JTAG, this signal can be left as a no connect.

 

 

 

 

 

 

 

TDO

 

O

 

Test Data Output: This is the serial data output from the JTAG BSCAN logic

 

 

 

If not utilizing JTAG, this signal can be left as a no connect.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test Mode Select: This signal controls the TAP controller state machine to

 

TMS

 

I

 

move to different states and is sampled on the rising edge of TCK.

 

 

 

 

 

If not utilizing JTAG, this signal can be left as a no connect.

 

 

 

 

 

 

 

 

 

 

 

Test Reset In: This signal is used to asynchronously reset the JTAG BSCAN

 

TRST#

 

I

 

logic.

 

 

 

If not utilizing JTAG, connect this signal to ground through a 1KΩ pull-down

 

 

 

 

 

 

 

 

 

 

resistor.

 

 

 

 

 

 

 

RESERVED[8:1]

 

I

 

Reserved: (8 pins) These input pins should be pulled low

 

 

 

Use an approximately 8.2KΩ resistor to pull-down to ground.

 

 

 

 

 

 

 

 

 

 

 

 

NC[19:18], NC[16:1]

 

 

 

No Connect: (39 pins) These output pins should be left floating

 

A_NC[10:1]

 

O

 

 

B_NC[10:1]

 

 

 

 

 

 

 

 

 

 

 

NC[17]

 

O

 

This signal requires an external pull-up, 8.2K ohm to 3.3V

 

 

 

 

 

 

 

Total

 

 

57

 

 

 

 

 

 

 

22

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Page 21 Page 23
Image 22
Page 21 Page 23
Contents Intel 41210 Serial to Parallel PCI Bridge Developer’s ManualIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Revision History Date Revision DescriptionPCI-X Interface Features PCI Express* Interface FeaturesIntroduction1 SMBus Interface Power ManagementJtag Signal Description On-Die Termination ODTADEVSEL# BDEVSEL# AFRAME# BFRAME# ODT SignalsAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 AGNT#50 BGNT#50PERCOMP10 PCI Express* Interface PinsPCI Express* Interface TotalADEVSEL# PCI Interface Pins Sheet 1PCI Bus Interface Two Instances AIRDY#PCI Interface Pins Sheet 2 PCI Clock and Reset Pins PCI Interface Pins 64-Bit ExtensionsPCI Bus Interface 64-Bit Extension Two Interfaces AINTA# AINTB# Interrupt Interface PinsInterrupt Interface Two Interfaces AINTC# AINTD#Reset Strap Pins Reset StrapsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsVoltage Pins Number DescriptionThis page Intentionally Left Blank Initialization PCI Mode Pin/Strap EncodingPCI-X Interface PCI-X Initialization PatternPCI Transactions Supported PCI ModeTransactions Supported Transaction Encoding1Read Transactions PCI-X ModePCI-X Transactions Supported Configuration Transactions DelayedEnd Point Source Lock CyclesPCI Decoding Transaction TerminationPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface 2 4 GB and 4 K Page Crossover PCI-X Protocol SpecificsAttributes Wait StatesFields ArbitrationSplit Transactions Split Completion Abort RegistersInternal Arbitration Scheme BridgeM0 High Priority Group Lpg Low Priority B3173-01Software-Driven PCI-PM 1.1-Compatible Power Management Power ManagementHardware-Controlled Active State Power Management PCI Bus Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank PCI-to-PCI Bridge B Configuration Space Addressable Space AccessPCI-to-PCI Bridge a Configuration Space Addressing5Device Number Signal Used for Public/Private Configuration-Space AccessPCI Express* Configuration Access Secondary PCI DevicesAddressing Type 0 Configuration Access from PCI-X Interface Type 1 to Type 0 Translation PCI and PCI-XI/O Space Access Mechanism SMBus Configuration AccessO Forwarding Memory Space Access Mechanism Memory-Mapped I/O Window Memory ForwardingPrefetchable Memory Window VGA AddressingOpaque Memory Window § § Upstream Transaction Ordering Transaction OrderingUpstream Transaction Ordering Row Pass ColumnRelaxed Ordering/No-Snoop Support Downstream Transaction OrderingDownstream Transaction Ordering Legacy Interrupt Sharing Interrupt SupportINTx Routing Table Device Number on Interrupt Routing for Devices behind a BridgeInterrupt Binding for Devices behind a Bridge Secondary BusSMBus Address Assignments System Management Bus InterfaceBit Value Internal Command SMBus CommandsSMBus Command Encoding SMBus commandInitialization Sequence ConfigurationSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clocking Clock and ResetDevice Reset Clock DomainsRSTIN# Reset Mechanism PERST# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank PCI Express* Errors Error HandlingPCI Errors Completion-Status Translation for Immediate Terminations Error TypesTermination of Completion Required Transactions PCI-X Termination PCI Express* CompletionIndex PCI-X Split Termination Message PCI ExpressSuccessful 00h Split Termination on PCI Express* Interface PCI Express* Completion Status PCI CompletionRegister Description Register Nomenclature and Access AttributesPERST# reset Bit Attribute DefinitionsConfiguration Registers 0xFFF 0x300 0x100 0x40 0x00 PCI/PCI-X Compatible Configuration regionCapptr B3174-02Legacy Configuration Space Register PCI Express* Extended Configuration SpaceByte Offset Reset Description Offset 04h PCICMD-Command RegisterOffset 04h PCICMD-Command Register Sheet 1 Offset 00h ID-IdentifiersOffset 06h PSTS-Primary Device Status Sheet 1 Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status TypeOffset 08h REVID-Revision ID Offset 08h REVID-Revision IDOffset 06h PSTS-Primary Device Status Sheet 2 BitsOffset 0Ch CLS-Cache-Line Size Offset 0Dh PMLT-Primary Master Latency TimerOffset 09h CC-Class Code Offset 0Eh HEADTYP-Header TypeOffset 18h BNUM-Bus Numbers Offset 1Bh SMLT-Secondary Master Latency TimerOffset 1Bh SMLT-Secondary Master Latency Timer Offset 18h BNUM-Bus NumbersFFFh Offset 1Ch IOBL-I/O Base and LimitOffset 1Ch IOBL-I/O Base and Limit Support for 16-bit I/O addressing onlyOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary Status3120 000h Offset 20h MBL-Memory Base and LimitOffset 20h MBL-Memory Base and Limit Must be less than this valueOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Bits Type Reset DescriptionOffset 24h PMBL-Prefetchable Memory Base and Limit Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 34h CAPP-Capabilities List Pointer Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 3Ch INTR-Interrupt InformationOffset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 1Offset 3Eh BCTRL-Bridge Control Sheet 2 Peer Memory Read Enable Pmre Offset 40h BCNF-Bridge Configuration RegisterOffset 40h BCNF-Bridge Configuration Register Bit Maximum Number of Upstream Delayed TransactionsOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 42h MTT-Multi-Transaction TimerOffset 43h PCLKC-PCI Clock Control Offset 45h EXPNXTP-Next Item PointerOffset 46h EXPCAP-PCI Express* Capability Default DescriptionOffset 46h EXPCAP-PCI Express* Capability Bit MaxReadRequestSize Offset 4Ch EXPDCTL-PCI Express* Device Control RegisterBit MaxPayloadSize Offset 50h EXPLCAP-PCI Express* Link Capabilities Register Offset 4Eh EXPDSTS-PCI Express* Device Status RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 54h EXPLCTL-PCI Express* Link Control Register Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit LatencyOffset 5Ch MSICAPID-PCI Express* MSI Capability Identifier Offset 56h EXPLSTS-PCI Express* Link Status RegisterOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 60h MSIMA-PCI Express* MSI Message Address Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 5Eh MSIMC-PCI Express* MSI Message Control Offset 68h MSIMD-PCI Express* MSI Message DataOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Eh PMPMC-Power Management Capabilities Offset 6Eh PMPMC-Power Management CapabilitiesOffset 72h PMBSE-Power Management Bridge Support Extensions Offset 70h PMPMCSR-Power Management Control/Status RegisterOffset 73h PMDATA-Power Management Data Field Offset D8h PXCAPID-PCI-X Capabilities Identifier Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D9h PXNXTP-PCI-X Next Item Pointer Offset D9h PXNXTP-PCI-X Next Item PointerOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset DCh PXBSTS-PCI-X Bridge Status Offset DCh PXBSTS-PCI-X Bridge StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterID, indicating Advanced Error Reporting Capability Power Budgeting Capability as the next capabilityAdvanced Error Reporting Extended Capability Version Number When the configuration unit signals a completer abortOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskData Link Protocol Error Severity Unsupported Request Error Status SeverityFlow Control Protocol Error Status Severity Training Error Severity Not supportedOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error MaskOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Sheet 2 Logs the headerPCI-X Uncorrectable Address Parity Error Detected Mask Internal Bridge Data Error MaskPCI Delayed Transaction Timer Expiry Mask PCI-X Uncorrectable Attribute Parity Error Detected MaskPCI-X Detected Target Abort Mask optional in specification PCI-X Detected Split Completion Master Abort MaskPCI-X Uncorrectable Address Parity Error Detected Severity Internal Bridge Data Error SeverityPCI Delayed Transaction Timer Expiry Severity PCI-X Uncorrectable Data Parity Error Detected SeverityPCI-X Detected Split Completion Master Abort Severity Rwcs = Errnonfatal = ErrfatalRegister is cleared by the software writing a 1 to the bit Offset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Type Reset DescriptionOffset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterReserved Read only Offset 170h SSR-Strap Status RegisterOffset 170h SSR-Strap Status Register SMBUS5 SMBUS3 SMBUS2 SMBUS1Offset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 308h PWRBGTDATA-Power Budgeting Data Register Offset 308h PWRBGTDATA-Power Budgeting Data Register
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