Intel 41210 manual PCI-X Mode, Read Transactions, PCI-X Transactions Supported

Page 27

PCI-X Interface

3.2.2PCI-X Mode

Table 14 lists the transactions that the 41210 supports when the PCI interface is in the PCI-X mode. As a master, the 41210 supports the memory write block command for writes that are multiples of cache-line.

Table 14.

PCI-X Transactions Supported

 

 

 

 

 

 

 

 

 

Transaction

Encoding1

Master

Target

 

Interrupt acknowledge

0000

No

No

 

 

 

 

 

 

Special cycle

0001

Yes

No

 

(PCI Express* Type1-to-PCI Special Cycle)

 

 

 

 

 

 

 

 

 

 

I/O read

0010

Yes

Yes

 

 

 

 

 

 

I/O write

0011

Yes

Yes

 

 

 

 

 

 

Reserved

0100

No

No

 

 

 

 

 

 

Reserved

0101

No

No

 

 

 

 

 

 

Memory read DWORD

0110

Yes

Yes

 

 

 

 

 

 

Memory write

0111

Yes

Yes

 

 

 

 

 

 

Alias to memory read block

1000

No

Yes

 

 

 

 

 

 

Alias to memory write block

1001

No

Yes

 

 

 

 

 

 

Configuration read

1010

Yes

Yes2

 

Configuration write

1011

Yes

Yes

 

 

 

 

 

 

Split completion

1100

Yes

Yes

 

 

 

 

 

 

Dual address cycle

1101

Yes

Yes

 

 

 

 

 

 

Memory read block

1110

Yes

Yes

 

 

 

 

 

 

Memory write block

1111

Yes

Yes

 

 

 

 

 

 

LOCK transaction

–

Yes

No

 

 

 

 

 

 

NOTES:

 

 

 

1.PCI command encodings that are not detailed in this table are ignored.

2.Upstream Type 0 configuration cycles to the bridge’s own configuration space are supported.

3.2.3Read Transactions

3.2.3.1Prefetchable

Any memory read line or memory read multiple commands on PCI that are decoded by the 41210 are prefetched on the PCI Express* interface. The prefetchability of a given PCI read request is determined by the prefetch policy (PP) bits[55:54] of the “Offset 178h: PREFCTRL—Prefetch Control Register” on page 119. The amount of data prefetched depends on the clock frequency, x_REQ64#, and the command type. The 41210 does not prefetch past a 4 KB page boundary.

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

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Contents Developer’s Manual Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Date Revision Description Revision HistoryPCI Express* Interface Features PCI-X Interface FeaturesIntroduction1 Power Management SMBus InterfaceJtag On-Die Termination ODT Signal DescriptionAGNT#50 BGNT#50 ODT SignalsAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 ADEVSEL# BDEVSEL# AFRAME# BFRAME#Total PCI Express* Interface PinsPCI Express* Interface PERCOMP10AIRDY# PCI Interface Pins Sheet 1PCI Bus Interface Two Instances ADEVSEL#PCI Interface Pins Sheet 2 PCI Interface Pins 64-Bit Extensions PCI Clock and Reset PinsPCI Bus Interface 64-Bit Extension Two Interfaces AINTC# AINTD# Interrupt Interface PinsInterrupt Interface Two Interfaces AINTA# AINTB#Reset Straps Reset Strap PinsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsNumber Description Voltage PinsThis page Intentionally Left Blank PCI-X Initialization Pattern PCI Mode Pin/Strap EncodingPCI-X Interface InitializationTransaction Encoding1 PCI ModeTransactions Supported PCI Transactions SupportedPCI-X Mode Read TransactionsPCI-X Transactions Supported Delayed Configuration TransactionsLock Cycles End Point SourcePCI Transaction Termination DecodingPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface Wait States PCI-X Protocol SpecificsAttributes 2 4 GB and 4 K Page CrossoverSplit Completion Abort Registers ArbitrationSplit Transactions FieldsBridgeM0 High Priority Group Lpg Low Priority B3173-01 Internal Arbitration SchemePCI Bus Power Management Power ManagementHardware-Controlled Active State Power Management Software-Driven PCI-PM 1.1-Compatible Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank Addressing5 Addressable Space AccessPCI-to-PCI Bridge a Configuration Space PCI-to-PCI Bridge B Configuration SpaceSecondary PCI Devices Configuration-Space AccessPCI Express* Configuration Access Device Number Signal Used for Public/PrivateAddressing Type 1 to Type 0 Translation PCI and PCI-X Type 0 Configuration Access from PCI-X InterfaceSMBus Configuration Access I/O Space Access MechanismO Forwarding Memory Space Access Mechanism Memory Forwarding Memory-Mapped I/O WindowVGA Addressing Prefetchable Memory WindowOpaque Memory Window § § Row Pass Column Transaction OrderingUpstream Transaction Ordering Upstream Transaction OrderingDownstream Transaction Ordering Relaxed Ordering/No-Snoop SupportDownstream Transaction Ordering Interrupt Support Legacy Interrupt SharingINTx Routing Table Secondary Bus Interrupt Routing for Devices behind a BridgeInterrupt Binding for Devices behind a Bridge Device Number onSystem Management Bus Interface SMBus Address AssignmentsBit Value SMBus command SMBus CommandsSMBus Command Encoding Internal CommandConfiguration Initialization SequenceSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clock Domains Clock and ResetDevice Reset ClockingPERST# Reset Mechanism RSTIN# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank Error Handling PCI Express* ErrorsPCI Errors PCI-X Termination PCI Express* Completion Error TypesTermination of Completion Required Transactions Completion-Status Translation for Immediate TerminationsPCI-X Split Termination Message PCI Express IndexSuccessful 00h PCI Express* Completion Status PCI Completion Split Termination on PCI Express* InterfaceBit Attribute Definitions Register Nomenclature and Access AttributesPERST# reset Register DescriptionConfiguration Registers B3174-02 PCI/PCI-X Compatible Configuration regionCapptr 0xFFF 0x300 0x100 0x40 0x00Legacy Configuration Space PCI Express* Extended Configuration Space RegisterByte Offset Offset 00h ID-Identifiers Offset 04h PCICMD-Command RegisterOffset 04h PCICMD-Command Register Sheet 1 Reset DescriptionType Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status Offset 06h PSTS-Primary Device Status Sheet 1Bits Offset 08h REVID-Revision IDOffset 06h PSTS-Primary Device Status Sheet 2 Offset 08h REVID-Revision IDOffset 0Eh HEADTYP-Header Type Offset 0Dh PMLT-Primary Master Latency TimerOffset 09h CC-Class Code Offset 0Ch CLS-Cache-Line SizeOffset 18h BNUM-Bus Numbers Offset 1Bh SMLT-Secondary Master Latency TimerOffset 1Bh SMLT-Secondary Master Latency Timer Offset 18h BNUM-Bus NumbersSupport for 16-bit I/O addressing only Offset 1Ch IOBL-I/O Base and LimitOffset 1Ch IOBL-I/O Base and Limit FFFhOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary StatusMust be less than this value Offset 20h MBL-Memory Base and LimitOffset 20h MBL-Memory Base and Limit 3120 000hOffset 24h PMBL-Prefetchable Memory Base and Limit Bits Type Reset DescriptionOffset 24h PMBL-Prefetchable Memory Base and Limit Offset 28h PMBU32-Prefetchable Memory Base Upper 32 BitsOffset 3Ch INTR-Interrupt Information Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 34h CAPP-Capabilities List PointerOffset 3Eh BCTRL-Bridge Control Sheet 1 Offset 3Eh BCTRL-Bridge ControlOffset 3Eh BCTRL-Bridge Control Sheet 2 Bit Maximum Number of Upstream Delayed Transactions Offset 40h BCNF-Bridge Configuration RegisterOffset 40h BCNF-Bridge Configuration Register Peer Memory Read Enable PmreOffset 45h EXPNXTP-Next Item Pointer Offset 42h MTT-Multi-Transaction TimerOffset 43h PCLKC-PCI Clock Control Offset 44h EXPCAPID-PCI Express* Capability IdentifierDefault Description Offset 46h EXPCAP-PCI Express* CapabilityOffset 46h EXPCAP-PCI Express* Capability Offset 4Ch EXPDCTL-PCI Express* Device Control Register Bit MaxReadRequestSizeBit MaxPayloadSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 50h EXPLCAP-PCI Express* Link Capabilities RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register L0s Exit Latency Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register Offset 54h EXPLCTL-PCI Express* Link Control RegisterOffset 56h EXPLSTS-PCI Express* Link Status Register Offset 5Ch MSICAPID-PCI Express* MSI Capability IdentifierOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 68h MSIMD-PCI Express* MSI Message Data Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 5Eh MSIMC-PCI Express* MSI Message Control Offset 60h MSIMA-PCI Express* MSI Message AddressOffset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 70h PMPMCSR-Power Management Control/Status Register Offset 72h PMBSE-Power Management Bridge Support ExtensionsOffset 73h PMDATA-Power Management Data Field Offset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterWhen the configuration unit signals a completer abort Power Budgeting Capability as the next capabilityAdvanced Error Reporting Extended Capability Version Number ID, indicating Advanced Error Reporting CapabilityOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskTraining Error Severity Not supported Unsupported Request Error Status SeverityFlow Control Protocol Error Status Severity Data Link Protocol Error SeverityOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error MaskOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Logs the header Sheet 2PCI-X Uncorrectable Attribute Parity Error Detected Mask Internal Bridge Data Error MaskPCI Delayed Transaction Timer Expiry Mask PCI-X Uncorrectable Address Parity Error Detected MaskPCI-X Detected Split Completion Master Abort Mask PCI-X Detected Target Abort Mask optional in specificationPCI-X Uncorrectable Data Parity Error Detected Severity Internal Bridge Data Error SeverityPCI Delayed Transaction Timer Expiry Severity PCI-X Uncorrectable Address Parity Error Detected SeverityRwcs = Errnonfatal = Errfatal PCI-X Detected Split Completion Master Abort SeverityRegister is cleared by the software writing a 1 to the bit Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Type Reset DescriptionOffset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header LogSMBUS5 SMBUS3 SMBUS2 SMBUS1 Offset 170h SSR-Strap Status RegisterOffset 170h SSR-Strap Status Register Reserved Read onlyOffset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register
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