Intel 41210 manual Offset FCh BINIT-Bridge Initialization Register

Page 104

Register Description

12.2.50Offset FCh: BINIT—Bridge Initialization Register

Table 84.

Offset FCh: BINIT—Bridge Initialization Register

 

 

 

 

 

Bits

 

Type

Reset

Description

 

 

 

 

 

31:5

 

RO

000 0000h

Reserved

 

 

 

 

 

 

 

 

 

Opaque Memory Window Enable: When this bit is set, the Intel® 41210 Serial to Parallel

 

 

 

 

PCI Bridge hard-codes certain address ranges to the secondary segment of each bridge.

 

 

 

 

The hard-coded address ranges are as follows:

 

 

 

 

• A[63:62] = 10 secondary side of A-segment

 

 

 

 

• A[63:63] = 11 secondary side of B-segment

 

 

 

 

This address range is forwarded from the primary to the corresponding secondary side and

4

 

RWS

0b

also is never forwarded from the secondary to the primary side, irrespective of the setting of

 

the prefetchable base and limit registers.

 

 

 

 

 

 

 

 

Note that even when the opaque memory window is enabled, the normal 41210 behavior

 

 

 

 

defined for the BME, MSE, and IOSE bits in the PCICMD register are still true (“Offset 04h:

 

 

 

 

PCICMD—Command Register” on page 78).

 

 

 

 

0 = Opaque Memory Window disabled

 

 

 

 

1 = Opaque Memory Window enabled

 

 

 

 

Each segment of the bridge uses the bit corresponding to that side.

 

 

 

 

 

 

 

 

 

Configuration Cycle Retry: When set, this bit results in a configuration retry response on

 

 

 

Varies with

the Intel® 41210 Serial to Parallel PCI Bridge for all Type 0 configuration transactions from

 

 

 

external

PCI Express* to the internal bridge registers.

3

 

RW

state of

When this bit is cleared, Type 0 transactions are completed normally to the internal 41210

 

CFGRETRY

bridge registers.

 

 

 

pin on rising

0 = Normal response to Type 0 configuration transactions

 

 

 

edge of

 

 

 

1 = Response to Type 0 configuration transaction is the Configuration Retry Response.

 

 

 

PERST#

 

 

 

 

Each segment of the bridge uses the bit corresponding to that side.

 

 

 

 

 

 

 

 

 

Device Hiding Enable: This bit enables hiding of devices on the secondary PCI bus:

 

 

 

 

0 = All downstream devices are visible to all requestors.

2

 

RWS

0b

1 = Device numbers 0 to 9 on the immediate secondary bus are hidden from downstream

 

 

 

 

configuration transactions. See Section 5.2, “Secondary PCI Devices” on page 42.

 

 

 

 

Each segment of the bridge uses the bit corresponding to that side.

 

 

 

 

 

 

 

 

 

Upstream Configuration Enable: This bit controls the behavior for upstream configuration

 

 

 

 

transactions allowing local initialization from the secondary PCI-X interface:

1

 

RWS

1b

0 = Upstream configuration transactions are not claimed.

 

 

 

 

1 = Upstream configuration transactions with AD[16] = 1 are claimed.

 

 

 

 

Each segment of the bridge uses the bit corresponding to that side.

 

 

 

 

 

0

 

RWS

1b

Upstream I/O Enable: When set, this bit enables I/O transactions from PCI. The I/O

 

transactions are enabled by default.

 

 

 

 

 

 

 

 

 

104

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Page 103 Page 105
Image 104
Page 103 Page 105
Contents Intel 41210 Serial to Parallel PCI Bridge Developer’s ManualIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Revision History Date Revision DescriptionIntroduction1 PCI Express* Interface FeaturesPCI-X Interface Features Jtag Power ManagementSMBus Interface Signal Description On-Die Termination ODTODT Signals AACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74ADEVSEL# BDEVSEL# AFRAME# BFRAME# AGNT#50 BGNT#50PCI Express* Interface Pins PCI Express* InterfacePERCOMP10 TotalPCI Interface Pins Sheet 1 PCI Bus Interface Two InstancesADEVSEL# AIRDY#PCI Interface Pins Sheet 2 PCI Bus Interface 64-Bit Extension Two Interfaces PCI Interface Pins 64-Bit ExtensionsPCI Clock and Reset Pins Interrupt Interface Pins Interrupt Interface Two InterfacesAINTA# AINTB# AINTC# AINTD#Cfgretry Reset StrapsReset Strap Pins SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsVoltage Pins Number DescriptionThis page Intentionally Left Blank PCI Mode Pin/Strap Encoding PCI-X InterfaceInitialization PCI-X Initialization PatternPCI Mode Transactions SupportedPCI Transactions Supported Transaction Encoding1PCI-X Transactions Supported PCI-X ModeRead Transactions Configuration Transactions DelayedPCI Lock CyclesEnd Point Source Decoding Transaction TerminationPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface PCI-X Protocol Specifics Attributes2 4 GB and 4 K Page Crossover Wait StatesArbitration Split TransactionsFields Split Completion Abort RegistersInternal Arbitration Scheme BridgeM0 High Priority Group Lpg Low Priority B3173-01Power Management Hardware-Controlled Active State Power ManagementSoftware-Driven PCI-PM 1.1-Compatible Power Management PCI Bus Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank Addressable Space Access PCI-to-PCI Bridge a Configuration SpacePCI-to-PCI Bridge B Configuration Space Addressing5Configuration-Space Access PCI Express* Configuration AccessDevice Number Signal Used for Public/Private Secondary PCI DevicesAddressing Type 0 Configuration Access from PCI-X Interface Type 1 to Type 0 Translation PCI and PCI-XI/O Space Access Mechanism SMBus Configuration AccessO Forwarding Memory Space Access Mechanism Memory-Mapped I/O Window Memory ForwardingOpaque Memory Window VGA AddressingPrefetchable Memory Window § § Transaction Ordering Upstream Transaction OrderingUpstream Transaction Ordering Row Pass ColumnDownstream Transaction Ordering Downstream Transaction OrderingRelaxed Ordering/No-Snoop Support INTx Routing Table Interrupt SupportLegacy Interrupt Sharing Interrupt Routing for Devices behind a Bridge Interrupt Binding for Devices behind a BridgeDevice Number on Secondary BusBit Value System Management Bus InterfaceSMBus Address Assignments SMBus Commands SMBus Command EncodingInternal Command SMBus commandSMBus Status Byte Encoding ConfigurationInitialization Sequence Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clock and Reset Device ResetClocking Clock DomainsPCI Express* Reset Mechanism PERST# Reset MechanismRSTIN# Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank PCI Errors Error HandlingPCI Express* Errors Error Types Termination of Completion Required TransactionsCompletion-Status Translation for Immediate Terminations PCI-X Termination PCI Express* CompletionSuccessful 00h PCI-X Split Termination Message PCI ExpressIndex Split Termination on PCI Express* Interface PCI Express* Completion Status PCI CompletionRegister Nomenclature and Access Attributes PERST# resetRegister Description Bit Attribute DefinitionsConfiguration Registers PCI/PCI-X Compatible Configuration region Capptr0xFFF 0x300 0x100 0x40 0x00 B3174-02Legacy Configuration Space Byte Offset PCI Express* Extended Configuration SpaceRegister Offset 04h PCICMD-Command Register Offset 04h PCICMD-Command Register Sheet 1Reset Description Offset 00h ID-IdentifiersOffset 04h PCICMD-Command Register Sheet 2 Offset 06h PSTS-Primary Device StatusOffset 06h PSTS-Primary Device Status Sheet 1 TypeOffset 08h REVID-Revision ID Offset 06h PSTS-Primary Device Status Sheet 2Offset 08h REVID-Revision ID BitsOffset 0Dh PMLT-Primary Master Latency Timer Offset 09h CC-Class CodeOffset 0Ch CLS-Cache-Line Size Offset 0Eh HEADTYP-Header TypeOffset 1Bh SMLT-Secondary Master Latency Timer Offset 1Bh SMLT-Secondary Master Latency TimerOffset 18h BNUM-Bus Numbers Offset 18h BNUM-Bus NumbersOffset 1Ch IOBL-I/O Base and Limit Offset 1Ch IOBL-I/O Base and LimitFFFh Support for 16-bit I/O addressing onlyOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary StatusOffset 20h MBL-Memory Base and Limit Offset 20h MBL-Memory Base and Limit3120 000h Must be less than this valueBits Type Reset Description Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 Bits Offset 30h IOBLU16-I/O Base and Limit Upper 16 BitsOffset 34h CAPP-Capabilities List Pointer Offset 3Ch INTR-Interrupt InformationOffset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 1Offset 3Eh BCTRL-Bridge Control Sheet 2 Offset 40h BCNF-Bridge Configuration Register Offset 40h BCNF-Bridge Configuration RegisterPeer Memory Read Enable Pmre Bit Maximum Number of Upstream Delayed TransactionsOffset 42h MTT-Multi-Transaction Timer Offset 43h PCLKC-PCI Clock ControlOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 45h EXPNXTP-Next Item PointerOffset 46h EXPCAP-PCI Express* Capability Default DescriptionOffset 46h EXPCAP-PCI Express* Capability Bit MaxPayloadSize Offset 4Ch EXPDCTL-PCI Express* Device Control RegisterBit MaxReadRequestSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 4Eh EXPDSTS-PCI Express* Device Status RegisterOffset 50h EXPLCAP-PCI Express* Link Capabilities Register Bits Type Default Description Offset 54h EXPLCTL-PCI Express* Link Control RegisterOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit LatencyOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 56h EXPLSTS-PCI Express* Link Status RegisterOffset 5Ch MSICAPID-PCI Express* MSI Capability Identifier Offset 6Ch PMCAPID-Power Management Capabilities Identifier Offset 5Eh MSIMC-PCI Express* MSI Message ControlOffset 60h MSIMA-PCI Express* MSI Message Address Offset 68h MSIMD-PCI Express* MSI Message DataOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management CapabilitiesOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management CapabilitiesOffset 73h PMDATA-Power Management Data Field Offset 70h PMPMCSR-Power Management Control/Status RegisterOffset 72h PMBSE-Power Management Bridge Support Extensions Offset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item PointerOffset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item PointerOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterPower Budgeting Capability as the next capability Advanced Error Reporting Extended Capability Version NumberID, indicating Advanced Error Reporting Capability When the configuration unit signals a completer abortOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskUnsupported Request Error Status Severity Flow Control Protocol Error Status SeverityData Link Protocol Error Severity Training Error Severity Not supportedOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask1270 Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header LogOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Sheet 1 Sheet 2 Logs the headerInternal Bridge Data Error Mask PCI Delayed Transaction Timer Expiry MaskPCI-X Uncorrectable Address Parity Error Detected Mask PCI-X Uncorrectable Attribute Parity Error Detected MaskPCI-X Detected Target Abort Mask optional in specification PCI-X Detected Split Completion Master Abort MaskInternal Bridge Data Error Severity PCI Delayed Transaction Timer Expiry SeverityPCI-X Uncorrectable Address Parity Error Detected Severity PCI-X Uncorrectable Data Parity Error Detected SeverityRegister is cleared by the software writing a 1 to the bit Rwcs = Errnonfatal = ErrfatalPCI-X Detected Split Completion Master Abort Severity Type Reset Description Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterOffset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterOffset 170h SSR-Strap Status Register Offset 170h SSR-Strap Status RegisterReserved Read only SMBUS5 SMBUS3 SMBUS2 SMBUS16360 RsvdP Offset 178h PREFCTRL-Prefetch Control RegisterOffset 178h PREFCTRL-Prefetch Control Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data RegisterOffset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data Register
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