12.2.6

		Contents
12.2.6	Offset 0Ch: CLS—Cache-Line Size	81
12.2.7	Offset 0Dh: PMLT—Primary Master Latency Timer	81
12.2.8	Offset 0Eh: HEADTYP—Header Type	81
12.2.9	Offset 18h: BNUM—Bus Numbers	82
12.2.10	Offset 1Bh: SMLT—Secondary Master Latency Timer	82
12.2.11	Offset 1Ch: IOBL—I/O Base and Limit	83
12.2.12	Offset 1Eh: SSTS—Secondary Status	84
12.2.13	Offset 20h: MBL—Memory Base and Limit	85
12.2.14	Offset 24h: PMBL—Prefetchable Memory Base and Limit	86
12.2.15	Offset 28h: PMBU32—Prefetchable Memory Base Upper 32 Bits	86
12.2.16	Offset 2Ch: PMLU32—Prefetchable Memory Limit Upper 32 Bits	87
12.2.17	Offset 30h: IOBLU16—I/O Base and Limit Upper 16 Bits	87
12.2.18	Offset 34h: CAPP—Capabilities List Pointer	87
12.2.19	Offset 3Ch: INTR—Interrupt Information	87
12.2.20	Offset 3Eh: BCTRL—Bridge Control	88
12.2.21	Offset 40h: BCNF—Bridge Configuration Register	90
12.2.22	Offset 42h: MTT—Multi-Transaction Timer	91
12.2.23	Offset 43h: PCLKC—PCI Clock Control	91
12.2.24	Offset 44h: EXP_CAPID—PCI Express* Capability Identifier	91
12.2.25	Offset 45h: EXP_NXTP—Next Item Pointer	91
12.2.26	Offset 46h: EXP_CAP—PCI Express* Capability	92
12.2.27	Offset 48h: EXP_DCAP—PCI Express* Device Capabilities Register	92
12.2.28	Offset 4Ch: EXP_DCTL—PCI Express* Device Control Register	93
12.2.29	Offset 4Eh: EXP_DSTS—PCI Express* Device Status Register	94
12.2.30	Offset 50h: EXP_LCAP—PCI Express* Link Capabilities Register	94
12.2.31	Offset 54h: EXP_LCTL—PCI Express* Link Control Register	95
12.2.32	Offset 56h: EXP_LSTS—PCI Express* Link Status Register	96
12.2.33	Offset 5Ch: MSI_CAPID—PCI Express* MSI Capability Identifier	96
12.2.34	Offset 5Dh: MSI_NXTP—PCI Express* Next Item Pointer	96
12.2.35	Offset 5Eh: MSI_MC—PCI Express* MSI Message Control	97
12.2.36	Offset 60h: MSI_MA—PCI Express* MSI Message Address	97
12.2.37	Offset 68h: MSI_MD—PCI Express* MSI Message Data	97
12.2.38	Offset 6Ch: PM_CAPID—Power Management Capabilities Identifier	97
12.2.39	Offset 6Dh: PM_NXTP—Power Management Next Item Pointer	98
12.2.40	Offset 6Eh: PM_PMC—Power Management Capabilities	98
12.2.41	Offset 70h: PM_PMCSR—Power Management Control/Status Register	99
12.2.42 Offset 72h: PM_BSE—Power Management Bridge
	Support Extensions	99
12.2.43 Offset 73h: PM_DATA—Power Management Data Field		99
12.2.44 Offset D8h: PX_CAPID—PCI-X Capabilities Identifier		100
12.2.45 Offset D9h: PX_NXTP—PCI-X Next Item Pointer		100
12.2.46 Offset DAh: PX_SSTS—PCI-X Secondary Status		101
12.2.47 Offset DCh: PX_BSTS—PCI-X Bridge Status		102
12.2.48 Offset E0h: PX_USTC—PCI-X Upstream Split Transaction Control		102
12.2.49 Offset E4h: PX_DSTC—PCI-X Downstream Split Transaction Control		103
12.2.50 Offset FCh: BINIT—Bridge Initialization Register		104
12.2.51 Offset 100h: EXPAERR_CAPID—PCI Express* Advanced
	Error Capability Identifier	105
12.2.52 Offset 104h: ERRUNC_STS—PCI Express* Uncorrectable
	Error Status Register	105

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

12.2.42 Offset 72h: PM_BSE—Power Management Bridge