Register Description |
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Table 93. | Offset 12Ch: | |||
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Bits |
| Type | Reset | Description |
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2 |
| RWCS | 0b | is the master of a request transaction on the PCI bus and it receives a target abort. The |
| 41210 logs the header for that transaction. This bit is also set when the bridge receives a | |||
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| condition is the command, address, and attribute portion of the Split Completion Message. |
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1 |
| RWCS | 0b | completion sent by the 41210 on the |
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| of the split completion. |
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0 |
| RWCS | 0b | sets this bit when a split completion sent by the 41210 on the |
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| 41210 logs the header. |
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112 | Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual |