Intel 41210 manual PERST# Reset Mechanism, RSTIN# Reset Mechanism, PCI Express* Reset Mechanism

Page 66

Clock and Reset

10.2.1PERST# Reset Mechanism

All the voltage sources in the system are tracked by a system component that asserts the PERST# signal only after all the voltages have been stable for some predetermined time. The 41210 receives the PERST# signal as an asynchronous input, meaning that there is no assumed relationship between the assertion or the de-assertion of PERST# and the reference clock. While the PERST# is de-asserted, the 41210 holds all logic in reset.

The PERST# reset clears all internal state machines and logic, and initializes all registers to their default states, including “sticky” error bits that are persistent through all other reset classes. To eliminate potential system-reliability problems, all devices are also required to either tristate their outputs or to drive them to safe levels during such a power-on reset.

The 41210 keeps PCIRST# asserted for a minimum of 320 ms after the deassertion of PERST#.

Refer to the PCI Express* Specification, Revision 1.0a for details of the relationship between PERST# assertion and the stability of the clocks and power at the inputs of the 41210.

10.2.2RSTIN# Reset Mechanism

As soon as the system is up and running, a full system reset may be required to recover from system-error conditions related to various device or subsystem failures. The RSTIN# reset mechanism is a hot-reset mechanism that accomplishes this recovery without clearing the “sticky” error-status bits which track the cause of the error conditions of the device or subsystem.

A hot reset can be initiated by asserting the RSTIN# signal. This signal is treated as an asynchronous input to the 41210, meaning that there is no assumed relationship between the host reference clock and the assertion or the de-assertion of RSTIN#.

When the 41210 goes through a reset due to RSTIN# assertion, the link goes down, which is interpreted by the upstream component as a surprise extraction which may cause system instability.

The 41210 keeps PCIRST# asserted for a minimum of 320 ms after the deassertion of RSTIN#.

10.2.3PCI Express* Reset Mechanism

There is no reset signal on the PCI Express*, and all reset communication is in-band. The upstream PCI Express* device communicates the fact that it is entering and coming out of a reset using messages. The 41210 responds by also going through a reset. In accordance with the PCI Express* protocol, this incoming message is asynchronous to the reference clock.

When the upstream device puts the 41210 Bridge in reset through the in-band reset mechanism, the 41210 resets its core and PCI interfaces. Sticky bits are reserved

The 41210 keeps PCIRST# asserted for a minimum of 320 ms after the deassertion of the PCI Express* in-band reset message.

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Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Page 65 Page 67
Image 66
Page 65 Page 67
Contents Intel 41210 Serial to Parallel PCI Bridge Developer’s ManualIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Revision History Date Revision DescriptionPCI Express* Interface Features PCI-X Interface FeaturesIntroduction1 Power Management SMBus InterfaceJtag Signal Description On-Die Termination ODTADEVSEL# BDEVSEL# AFRAME# BFRAME# ODT SignalsAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 AGNT#50 BGNT#50PERCOMP10 PCI Express* Interface PinsPCI Express* Interface TotalADEVSEL# PCI Interface Pins Sheet 1PCI Bus Interface Two Instances AIRDY#PCI Interface Pins Sheet 2 PCI Interface Pins 64-Bit Extensions PCI Clock and Reset PinsPCI Bus Interface 64-Bit Extension Two Interfaces AINTA# AINTB# Interrupt Interface PinsInterrupt Interface Two Interfaces AINTC# AINTD#Reset Straps Reset Strap PinsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsVoltage Pins Number DescriptionThis page Intentionally Left Blank Initialization PCI Mode Pin/Strap EncodingPCI-X Interface PCI-X Initialization PatternPCI Transactions Supported PCI ModeTransactions Supported Transaction Encoding1PCI-X Mode Read TransactionsPCI-X Transactions Supported Configuration Transactions DelayedLock Cycles End Point SourcePCI Decoding Transaction TerminationPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface 2 4 GB and 4 K Page Crossover PCI-X Protocol SpecificsAttributes Wait StatesFields ArbitrationSplit Transactions Split Completion Abort RegistersInternal Arbitration Scheme BridgeM0 High Priority Group Lpg Low Priority B3173-01Software-Driven PCI-PM 1.1-Compatible Power Management Power ManagementHardware-Controlled Active State Power Management PCI Bus Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank PCI-to-PCI Bridge B Configuration Space Addressable Space AccessPCI-to-PCI Bridge a Configuration Space Addressing5Device Number Signal Used for Public/Private Configuration-Space AccessPCI Express* Configuration Access Secondary PCI DevicesAddressing Type 0 Configuration Access from PCI-X Interface Type 1 to Type 0 Translation PCI and PCI-XI/O Space Access Mechanism SMBus Configuration AccessO Forwarding Memory Space Access Mechanism Memory-Mapped I/O Window Memory ForwardingVGA Addressing Prefetchable Memory WindowOpaque Memory Window § § Upstream Transaction Ordering Transaction OrderingUpstream Transaction Ordering Row Pass ColumnDownstream Transaction Ordering Relaxed Ordering/No-Snoop SupportDownstream Transaction Ordering Interrupt Support Legacy Interrupt SharingINTx Routing Table Device Number on Interrupt Routing for Devices behind a BridgeInterrupt Binding for Devices behind a Bridge Secondary BusSystem Management Bus Interface SMBus Address AssignmentsBit Value Internal Command SMBus CommandsSMBus Command Encoding SMBus commandConfiguration Initialization SequenceSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clocking Clock and ResetDevice Reset Clock DomainsPERST# Reset Mechanism RSTIN# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank Error Handling PCI Express* ErrorsPCI Errors Completion-Status Translation for Immediate Terminations Error TypesTermination of Completion Required Transactions PCI-X Termination PCI Express* CompletionPCI-X Split Termination Message PCI Express IndexSuccessful 00h Split Termination on PCI Express* Interface PCI Express* Completion Status PCI CompletionRegister Description Register Nomenclature and Access AttributesPERST# reset Bit Attribute DefinitionsConfiguration Registers 0xFFF 0x300 0x100 0x40 0x00 PCI/PCI-X Compatible Configuration regionCapptr B3174-02Legacy Configuration Space PCI Express* Extended Configuration Space RegisterByte Offset Reset Description Offset 04h PCICMD-Command RegisterOffset 04h PCICMD-Command Register Sheet 1 Offset 00h ID-IdentifiersOffset 06h PSTS-Primary Device Status Sheet 1 Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status TypeOffset 08h REVID-Revision ID Offset 08h REVID-Revision IDOffset 06h PSTS-Primary Device Status Sheet 2 BitsOffset 0Ch CLS-Cache-Line Size Offset 0Dh PMLT-Primary Master Latency TimerOffset 09h CC-Class Code Offset 0Eh HEADTYP-Header TypeOffset 18h BNUM-Bus Numbers Offset 1Bh SMLT-Secondary Master Latency TimerOffset 1Bh SMLT-Secondary Master Latency Timer Offset 18h BNUM-Bus NumbersFFFh Offset 1Ch IOBL-I/O Base and LimitOffset 1Ch IOBL-I/O Base and Limit Support for 16-bit I/O addressing onlyOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary Status3120 000h Offset 20h MBL-Memory Base and LimitOffset 20h MBL-Memory Base and Limit Must be less than this valueOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Bits Type Reset DescriptionOffset 24h PMBL-Prefetchable Memory Base and Limit Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 34h CAPP-Capabilities List Pointer Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 3Ch INTR-Interrupt InformationOffset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 1Offset 3Eh BCTRL-Bridge Control Sheet 2 Peer Memory Read Enable Pmre Offset 40h BCNF-Bridge Configuration RegisterOffset 40h BCNF-Bridge Configuration Register Bit Maximum Number of Upstream Delayed TransactionsOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 42h MTT-Multi-Transaction TimerOffset 43h PCLKC-PCI Clock Control Offset 45h EXPNXTP-Next Item PointerDefault Description Offset 46h EXPCAP-PCI Express* CapabilityOffset 46h EXPCAP-PCI Express* Capability Offset 4Ch EXPDCTL-PCI Express* Device Control Register Bit MaxReadRequestSizeBit MaxPayloadSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 50h EXPLCAP-PCI Express* Link Capabilities RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 54h EXPLCTL-PCI Express* Link Control Register Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit LatencyOffset 56h EXPLSTS-PCI Express* Link Status Register Offset 5Ch MSICAPID-PCI Express* MSI Capability IdentifierOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 60h MSIMA-PCI Express* MSI Message Address Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 5Eh MSIMC-PCI Express* MSI Message Control Offset 68h MSIMD-PCI Express* MSI Message DataOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Eh PMPMC-Power Management Capabilities Offset 6Eh PMPMC-Power Management CapabilitiesOffset 70h PMPMCSR-Power Management Control/Status Register Offset 72h PMBSE-Power Management Bridge Support ExtensionsOffset 73h PMDATA-Power Management Data Field Offset D8h PXCAPID-PCI-X Capabilities Identifier Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D9h PXNXTP-PCI-X Next Item Pointer Offset D9h PXNXTP-PCI-X Next Item PointerOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset DCh PXBSTS-PCI-X Bridge Status Offset DCh PXBSTS-PCI-X Bridge StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterID, indicating Advanced Error Reporting Capability Power Budgeting Capability as the next capabilityAdvanced Error Reporting Extended Capability Version Number When the configuration unit signals a completer abortOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskData Link Protocol Error Severity Unsupported Request Error Status SeverityFlow Control Protocol Error Status Severity Training Error Severity Not supportedOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error MaskOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Sheet 2 Logs the headerPCI-X Uncorrectable Address Parity Error Detected Mask Internal Bridge Data Error MaskPCI Delayed Transaction Timer Expiry Mask PCI-X Uncorrectable Attribute Parity Error Detected MaskPCI-X Detected Target Abort Mask optional in specification PCI-X Detected Split Completion Master Abort MaskPCI-X Uncorrectable Address Parity Error Detected Severity Internal Bridge Data Error SeverityPCI Delayed Transaction Timer Expiry Severity PCI-X Uncorrectable Data Parity Error Detected SeverityRwcs = Errnonfatal = Errfatal PCI-X Detected Split Completion Master Abort SeverityRegister is cleared by the software writing a 1 to the bit Offset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Type Reset DescriptionOffset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterReserved Read only Offset 170h SSR-Strap Status RegisterOffset 170h SSR-Strap Status Register SMBUS5 SMBUS3 SMBUS2 SMBUS1Offset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 308h PWRBGTDATA-Power Budgeting Data Register Offset 308h PWRBGTDATA-Power Budgeting Data Register
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