Intel 41210 manual Power-Management Event Signaling

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Power Management

4.4Intel® 41210 Serial to Parallel PCI Bridge Device Power Management

Each bridge segment supports PCI-PM 1.1 device power management states D0, D3hot, and D3cold. Each function, when programmed to the D3hot state, behaves as follows:

•The function responds to configuration cycles from PCI Express*.

•The function initiates and accepts PCI Express* completion transactions.

•The function does not respond to memory cycles on PCI Express*.

•The function does not respond to I/O cycles on PCI Express*.

•The function does not initiate PCI Express* request transactions.

•The function does not reset its registers, when programmed to D0 from D3hot.

•The 41210 does not assert PCIRST# when in the D3hot state.

4.5Power-Management Event Signaling

The 41210 supports conveying PCI power-management events (PME#) over PCI Express* by means of an in-band mechanism. Power-management events are generated on behalf of PCI devices that require a change in their power state. The 41210 does not support any method to “wake” the PCI Express* hierarchy before it signals a PME message (in other words, the 41210 supports neither the WAKE# side band signal nor the in-band tone-generation mechanism). Waking is needed when the upstream component is in a non-communicative state with clock and/or power removed. The expectation for this component is that both ends of the link are fully powered and clocked (in other words, the link is fully communicative) when signaling the PCI power- management events.

The 41210 supports a PME# event pin for conveying power-management events that occur on the secondary PCI bus segments of the 41210. The PME output from all the PCI devices on the segment are wire-ORed to obtain a composite PME signal which is routed to the 41210. The 41210 converts the level-sensitive PME# signal into a PCI Express* message. This message carries the bus number of the PCI bus that caused the PME# assertion. The power-manager software needs the bus-number information when invoked.

Note: Since the bus number of the PCI bus must be passed in the PME_MSG, this scheme functions correctly only for waking from the PCI buses directly below the 41210.

The exact mechanism for generating the PME_MSG packet in the 41210 involves sending a message over PCI Express* whenever the PME input pin is asserted. Note that this packet must carry the bus number of the PCI bus generating the PME#. This means that the 41210 must construct the requestor ID of the PME_MSG packet with the secondary bus-number register in the corresponding PCI-to-PCI Bridge header space. There is a chance that PME messages could be lost. Thus the 41210 implements a counter to periodically sample the PME# pin and generate a message. Refer to the PCI Express* specifications for more details. This polling mechanism creates spurious interrupts to the power-manager software, and the power manager must be able to handle this.

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Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

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Contents Intel 41210 Serial to Parallel PCI Bridge Developer’s ManualIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Revision History Date Revision DescriptionIntroduction1 PCI Express* Interface FeaturesPCI-X Interface Features Jtag Power ManagementSMBus Interface Signal Description On-Die Termination ODTADEVSEL# BDEVSEL# AFRAME# BFRAME# ODT SignalsAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 AGNT#50 BGNT#50PERCOMP10 PCI Express* Interface PinsPCI Express* Interface TotalADEVSEL# PCI Interface Pins Sheet 1PCI Bus Interface Two Instances AIRDY#PCI Interface Pins Sheet 2 PCI Bus Interface 64-Bit Extension Two Interfaces PCI Interface Pins 64-Bit ExtensionsPCI Clock and Reset Pins AINTA# AINTB# Interrupt Interface PinsInterrupt Interface Two Interfaces AINTC# AINTD#Cfgretry Reset StrapsReset Strap Pins SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsVoltage Pins Number DescriptionThis page Intentionally Left Blank Initialization PCI Mode Pin/Strap EncodingPCI-X Interface PCI-X Initialization PatternPCI Transactions Supported PCI ModeTransactions Supported Transaction Encoding1PCI-X Transactions Supported PCI-X ModeRead Transactions Configuration Transactions DelayedPCI Lock CyclesEnd Point Source Decoding Transaction TerminationPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface 2 4 GB and 4 K Page Crossover PCI-X Protocol SpecificsAttributes Wait StatesFields ArbitrationSplit Transactions Split Completion Abort RegistersInternal Arbitration Scheme BridgeM0 High Priority Group Lpg Low Priority B3173-01Software-Driven PCI-PM 1.1-Compatible Power Management Power ManagementHardware-Controlled Active State Power Management PCI Bus Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank PCI-to-PCI Bridge B Configuration Space Addressable Space AccessPCI-to-PCI Bridge a Configuration Space Addressing5Device Number Signal Used for Public/Private Configuration-Space AccessPCI Express* Configuration Access Secondary PCI DevicesAddressing Type 0 Configuration Access from PCI-X Interface Type 1 to Type 0 Translation PCI and PCI-XI/O Space Access Mechanism SMBus Configuration AccessO Forwarding Memory Space Access Mechanism Memory-Mapped I/O Window Memory ForwardingOpaque Memory Window VGA AddressingPrefetchable Memory Window § § Upstream Transaction Ordering Transaction OrderingUpstream Transaction Ordering Row Pass ColumnDownstream Transaction Ordering Downstream Transaction OrderingRelaxed Ordering/No-Snoop Support INTx Routing Table Interrupt SupportLegacy Interrupt Sharing Device Number on Interrupt Routing for Devices behind a BridgeInterrupt Binding for Devices behind a Bridge Secondary BusBit Value System Management Bus InterfaceSMBus Address Assignments Internal Command SMBus CommandsSMBus Command Encoding SMBus commandSMBus Status Byte Encoding ConfigurationInitialization Sequence Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clocking Clock and ResetDevice Reset Clock DomainsPCI Express* Reset Mechanism PERST# Reset MechanismRSTIN# Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank PCI Errors Error HandlingPCI Express* Errors Completion-Status Translation for Immediate Terminations Error TypesTermination of Completion Required Transactions PCI-X Termination PCI Express* CompletionSuccessful 00h PCI-X Split Termination Message PCI ExpressIndex Split Termination on PCI Express* Interface PCI Express* Completion Status PCI CompletionRegister Description Register Nomenclature and Access AttributesPERST# reset Bit Attribute DefinitionsConfiguration Registers 0xFFF 0x300 0x100 0x40 0x00 PCI/PCI-X Compatible Configuration regionCapptr B3174-02Legacy Configuration Space Byte Offset PCI Express* Extended Configuration SpaceRegister Reset Description Offset 04h PCICMD-Command RegisterOffset 04h PCICMD-Command Register Sheet 1 Offset 00h ID-IdentifiersOffset 06h PSTS-Primary Device Status Sheet 1 Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status TypeOffset 08h REVID-Revision ID Offset 08h REVID-Revision IDOffset 06h PSTS-Primary Device Status Sheet 2 BitsOffset 0Ch CLS-Cache-Line Size Offset 0Dh PMLT-Primary Master Latency TimerOffset 09h CC-Class Code Offset 0Eh HEADTYP-Header TypeOffset 18h BNUM-Bus Numbers Offset 1Bh SMLT-Secondary Master Latency TimerOffset 1Bh SMLT-Secondary Master Latency Timer Offset 18h BNUM-Bus NumbersFFFh Offset 1Ch IOBL-I/O Base and LimitOffset 1Ch IOBL-I/O Base and Limit Support for 16-bit I/O addressing onlyOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary Status3120 000h Offset 20h MBL-Memory Base and LimitOffset 20h MBL-Memory Base and Limit Must be less than this valueOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Bits Type Reset DescriptionOffset 24h PMBL-Prefetchable Memory Base and Limit Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 34h CAPP-Capabilities List Pointer Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 3Ch INTR-Interrupt InformationOffset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 1Offset 3Eh BCTRL-Bridge Control Sheet 2 Peer Memory Read Enable Pmre Offset 40h BCNF-Bridge Configuration RegisterOffset 40h BCNF-Bridge Configuration Register Bit Maximum Number of Upstream Delayed TransactionsOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 42h MTT-Multi-Transaction TimerOffset 43h PCLKC-PCI Clock Control Offset 45h EXPNXTP-Next Item PointerOffset 46h EXPCAP-PCI Express* Capability Default DescriptionOffset 46h EXPCAP-PCI Express* Capability Bit MaxPayloadSize Offset 4Ch EXPDCTL-PCI Express* Device Control RegisterBit MaxReadRequestSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 4Eh EXPDSTS-PCI Express* Device Status RegisterOffset 50h EXPLCAP-PCI Express* Link Capabilities Register Offset 54h EXPLCTL-PCI Express* Link Control Register Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit LatencyOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 56h EXPLSTS-PCI Express* Link Status RegisterOffset 5Ch MSICAPID-PCI Express* MSI Capability Identifier Offset 60h MSIMA-PCI Express* MSI Message Address Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 5Eh MSIMC-PCI Express* MSI Message Control Offset 68h MSIMD-PCI Express* MSI Message DataOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Eh PMPMC-Power Management Capabilities Offset 6Eh PMPMC-Power Management CapabilitiesOffset 73h PMDATA-Power Management Data Field Offset 70h PMPMCSR-Power Management Control/Status RegisterOffset 72h PMBSE-Power Management Bridge Support Extensions Offset D8h PXCAPID-PCI-X Capabilities Identifier Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D9h PXNXTP-PCI-X Next Item Pointer Offset D9h PXNXTP-PCI-X Next Item PointerOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset DCh PXBSTS-PCI-X Bridge Status Offset DCh PXBSTS-PCI-X Bridge StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterID, indicating Advanced Error Reporting Capability Power Budgeting Capability as the next capabilityAdvanced Error Reporting Extended Capability Version Number When the configuration unit signals a completer abortOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskData Link Protocol Error Severity Unsupported Request Error Status SeverityFlow Control Protocol Error Status Severity Training Error Severity Not supportedOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask1270 Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header LogOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Sheet 1 Sheet 2 Logs the headerPCI-X Uncorrectable Address Parity Error Detected Mask Internal Bridge Data Error MaskPCI Delayed Transaction Timer Expiry Mask PCI-X Uncorrectable Attribute Parity Error Detected MaskPCI-X Detected Target Abort Mask optional in specification PCI-X Detected Split Completion Master Abort MaskPCI-X Uncorrectable Address Parity Error Detected Severity Internal Bridge Data Error SeverityPCI Delayed Transaction Timer Expiry Severity PCI-X Uncorrectable Data Parity Error Detected SeverityRegister is cleared by the software writing a 1 to the bit Rwcs = Errnonfatal = ErrfatalPCI-X Detected Split Completion Master Abort Severity Offset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Type Reset DescriptionOffset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterReserved Read only Offset 170h SSR-Strap Status RegisterOffset 170h SSR-Strap Status Register SMBUS5 SMBUS3 SMBUS2 SMBUS16360 RsvdP Offset 178h PREFCTRL-Prefetch Control RegisterOffset 178h PREFCTRL-Prefetch Control Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 308h PWRBGTDATA-Power Budgeting Data Register Offset 308h PWRBGTDATA-Power Budgeting Data Register
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