Intel
41210
manual
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Signal Description
Error Handling
Delayed
Configuration-Space Access
PCI Clock and Reset Pins
Addressable Space Access
SMBus Commands
PCI Express* Interface Pins
Power Management
PCI-X Interface Features
Page 64
Local Initialization
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Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
Page 63
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Contents
Intel 41210 Serial to Parallel PCI Bridge
Developer’s Manual
Intel 41210 Serial to Parallel PCI Bridge Developer’s Manual
Contents
10.1
12.2.6
Figures
Tables
118
Offset 178h PREFCTRL-Prefetch Control Register
Revision History
Date Revision Description
PCI-X Interface Features
PCI Express* Interface Features
Introduction1
SMBus Interface
Power Management
Jtag
Signal Description
On-Die Termination ODT
ODT Signals
AACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74
ADEVSEL# BDEVSEL# AFRAME# BFRAME#
AGNT#50 BGNT#50
PCI Express* Interface Pins
PCI Express* Interface
PERCOMP10
Total
PCI Interface Pins Sheet 1
PCI Bus Interface Two Instances
ADEVSEL#
AIRDY#
PCI Interface Pins Sheet 2
PCI Clock and Reset Pins
PCI Interface Pins 64-Bit Extensions
PCI Bus Interface 64-Bit Extension Two Interfaces
Interrupt Interface Pins
Interrupt Interface Two Interfaces
AINTA# AINTB#
AINTC# AINTD#
Reset Strap Pins
Reset Straps
Cfgretry
SMBus Interface Pins
Miscellaneous Pins
Miscellaneous Pins
Voltage Pins
Number Description
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PCI Mode Pin/Strap Encoding
PCI-X Interface
Initialization
PCI-X Initialization Pattern
PCI Mode
Transactions Supported
PCI Transactions Supported
Transaction Encoding1
Read Transactions
PCI-X Mode
PCI-X Transactions Supported
Configuration Transactions
Delayed
End Point Source
Lock Cycles
PCI
Decoding
Transaction Termination
PCI-X Interface
PCI-X Mode Transaction Termination
PCI-X Interface
PCI-X Protocol Specifics
Attributes
2 4 GB and 4 K Page Crossover
Wait States
Arbitration
Split Transactions
Fields
Split Completion Abort Registers
Internal Arbitration Scheme
BridgeM0 High Priority Group Lpg Low Priority B3173-01
Power Management
Hardware-Controlled Active State Power Management
Software-Driven PCI-PM 1.1-Compatible Power Management
PCI Bus Power Management
Power-Management Event Signaling
Pmetoack
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Addressable Space Access
PCI-to-PCI Bridge a Configuration Space
PCI-to-PCI Bridge B Configuration Space
Addressing5
Configuration-Space Access
PCI Express* Configuration Access
Device Number Signal Used for Public/Private
Secondary PCI Devices
Addressing
Type 0 Configuration Access from PCI-X Interface
Type 1 to Type 0 Translation PCI and PCI-X
I/O Space Access Mechanism
SMBus Configuration Access
O Forwarding
Memory Space Access Mechanism
Memory-Mapped I/O Window
Memory Forwarding
Prefetchable Memory Window
VGA Addressing
Opaque Memory Window
§ §
Transaction Ordering
Upstream Transaction Ordering
Upstream Transaction Ordering
Row Pass Column
Relaxed Ordering/No-Snoop Support
Downstream Transaction Ordering
Downstream Transaction Ordering
Legacy Interrupt Sharing
Interrupt Support
INTx Routing Table
Interrupt Routing for Devices behind a Bridge
Interrupt Binding for Devices behind a Bridge
Device Number on
Secondary Bus
SMBus Address Assignments
System Management Bus Interface
Bit Value
SMBus Commands
SMBus Command Encoding
Internal Command
SMBus command
Initialization Sequence
Configuration
SMBus Status Byte Encoding
Clock Stretch
Clock Stretch
Configuration Writes
Error Handling
SMBus Interface Reset
Local Initialization
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Clock and Reset
Device Reset
Clocking
Clock Domains
RSTIN# Reset Mechanism
PERST# Reset Mechanism
PCI Express* Reset Mechanism
Software PCI Reset SBR-Secondary Bus Reset
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PCI Express* Errors
Error Handling
PCI Errors
Error Types
Termination of Completion Required Transactions
Completion-Status Translation for Immediate Terminations
PCI-X Termination PCI Express* Completion
Index
PCI-X Split Termination Message PCI Express
Successful 00h
Split Termination on PCI Express* Interface
PCI Express* Completion Status PCI Completion
Register Nomenclature and Access Attributes
PERST# reset
Register Description
Bit Attribute Definitions
Configuration Registers
PCI/PCI-X Compatible Configuration region
Capptr
0xFFF 0x300 0x100 0x40 0x00
B3174-02
Legacy Configuration Space
Register
PCI Express* Extended Configuration Space
Byte Offset
Offset 04h PCICMD-Command Register
Offset 04h PCICMD-Command Register Sheet 1
Reset Description
Offset 00h ID-Identifiers
Offset 04h PCICMD-Command Register Sheet 2
Offset 06h PSTS-Primary Device Status
Offset 06h PSTS-Primary Device Status Sheet 1
Type
Offset 08h REVID-Revision ID
Offset 06h PSTS-Primary Device Status Sheet 2
Offset 08h REVID-Revision ID
Bits
Offset 0Dh PMLT-Primary Master Latency Timer
Offset 09h CC-Class Code
Offset 0Ch CLS-Cache-Line Size
Offset 0Eh HEADTYP-Header Type
Offset 1Bh SMLT-Secondary Master Latency Timer
Offset 1Bh SMLT-Secondary Master Latency Timer
Offset 18h BNUM-Bus Numbers
Offset 18h BNUM-Bus Numbers
Offset 1Ch IOBL-I/O Base and Limit
Offset 1Ch IOBL-I/O Base and Limit
FFFh
Support for 16-bit I/O addressing only
Offset 1Eh SSTS-Secondary Status
Offset 1Eh SSTS-Secondary Status
Offset 20h MBL-Memory Base and Limit
Offset 20h MBL-Memory Base and Limit
3120 000h
Must be less than this value
Bits Type Reset Description
Offset 24h PMBL-Prefetchable Memory Base and Limit
Offset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits
Offset 24h PMBL-Prefetchable Memory Base and Limit
Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 Bits
Offset 30h IOBLU16-I/O Base and Limit Upper 16 Bits
Offset 34h CAPP-Capabilities List Pointer
Offset 3Ch INTR-Interrupt Information
Offset 3Eh BCTRL-Bridge Control
Offset 3Eh BCTRL-Bridge Control Sheet 1
Offset 3Eh BCTRL-Bridge Control Sheet 2
Offset 40h BCNF-Bridge Configuration Register
Offset 40h BCNF-Bridge Configuration Register
Peer Memory Read Enable Pmre
Bit Maximum Number of Upstream Delayed Transactions
Offset 42h MTT-Multi-Transaction Timer
Offset 43h PCLKC-PCI Clock Control
Offset 44h EXPCAPID-PCI Express* Capability Identifier
Offset 45h EXPNXTP-Next Item Pointer
Offset 46h EXPCAP-PCI Express* Capability
Default Description
Offset 46h EXPCAP-PCI Express* Capability
Bit MaxReadRequestSize
Offset 4Ch EXPDCTL-PCI Express* Device Control Register
Bit MaxPayloadSize
Offset 50h EXPLCAP-PCI Express* Link Capabilities Register
Offset 4Eh EXPDSTS-PCI Express* Device Status Register
Offset 4Eh EXPDSTS-PCI Express* Device Status Register
Bits Type Default Description
Offset 54h EXPLCTL-PCI Express* Link Control Register
Offset 54h EXPLCTL-PCI Express* Link Control Register
L0s Exit Latency
Offset 5Ch MSICAPID-PCI Express* MSI Capability Identifier
Offset 56h EXPLSTS-PCI Express* Link Status Register
Offset 5Dh MSINXTP-PCI Express* Next Item Pointer
Offset 6Ch PMCAPID-Power Management Capabilities Identifier
Offset 5Eh MSIMC-PCI Express* MSI Message Control
Offset 60h MSIMA-PCI Express* MSI Message Address
Offset 68h MSIMD-PCI Express* MSI Message Data
Offset 6Dh PMNXTP-Power Management Next Item Pointer
Offset 6Eh PMPMC-Power Management Capabilities
Offset 6Dh PMNXTP-Power Management Next Item Pointer
Offset 6Eh PMPMC-Power Management Capabilities
Offset 72h PMBSE-Power Management Bridge Support Extensions
Offset 70h PMPMCSR-Power Management Control/Status Register
Offset 73h PMDATA-Power Management Data Field
Offset D8h PXCAPID-PCI-X Capabilities Identifier
Offset D9h PXNXTP-PCI-X Next Item Pointer
Offset D8h PXCAPID-PCI-X Capabilities Identifier
Offset D9h PXNXTP-PCI-X Next Item Pointer
Offset DAh PXSSTS-PCI-X Secondary Status
Offset DAh PXSSTS-PCI-X Secondary Status
Offset DCh PXBSTS-PCI-X Bridge Status
Offset E0h PXUSTC-PCI-X Upstream Split Transaction Control
Offset DCh PXBSTS-PCI-X Bridge Status
Offset E0h PXUSTC-PCI-X Upstream Split Transaction Control
Offset E4h PXDSTC-PCI-X Downstream Split Transaction Control
Offset FCh BINIT-Bridge Initialization Register
Offset FCh BINIT-Bridge Initialization Register
Power Budgeting Capability as the next capability
Advanced Error Reporting Extended Capability Version Number
ID, indicating Advanced Error Reporting Capability
When the configuration unit signals a completer abort
Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask
Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask
Unsupported Request Error Status Severity
Flow Control Protocol Error Status Severity
Data Link Protocol Error Severity
Training Error Severity Not supported
Offset 110h ERRCORSTS-PCI Express* Correctable Error Status
Offset 110h ERRCORSTS-PCI Express* Correctable Error Status
Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask
Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask
Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log
Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log
1270
Sheet 1
Sheet 2
Logs the header
Internal Bridge Data Error Mask
PCI Delayed Transaction Timer Expiry Mask
PCI-X Uncorrectable Address Parity Error Detected Mask
PCI-X Uncorrectable Attribute Parity Error Detected Mask
PCI-X Detected Target Abort Mask optional in specification
PCI-X Detected Split Completion Master Abort Mask
Internal Bridge Data Error Severity
PCI Delayed Transaction Timer Expiry Severity
PCI-X Uncorrectable Address Parity Error Detected Severity
PCI-X Uncorrectable Data Parity Error Detected Severity
PCI-X Detected Split Completion Master Abort Severity
Rwcs = Errnonfatal = Errfatal
Register is cleared by the software writing a 1 to the bit
Type Reset Description
Offset 16Ah ARBCNTRL-Internal Arbiter Control Register
Offset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log
Offset 16Ah ARBCNTRL-Internal Arbiter Control Register
Offset 170h SSR-Strap Status Register
Offset 170h SSR-Strap Status Register
Reserved Read only
SMBUS5 SMBUS3 SMBUS2 SMBUS1
Offset 178h PREFCTRL-Prefetch Control Register
Offset 178h PREFCTRL-Prefetch Control Register
6360 RsvdP
Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register
Offset 308h PWRBGTDATA-Power Budgeting Data Register
Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register
Offset 308h PWRBGTDATA-Power Budgeting Data Register
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