Intel 41210 manual 3120 300h, Power Budgeting Capability as the next capability, 3121, Performed

Page 105

Register Description

12.2.51Offset 100h: EXPAERR_CAPID—PCI Express* Advanced Error Capability Identifier

This register stores the PCI Express* extended capability ID value.

Table 85.

Offset 100h: EXPAERR_CAPID—PCI Express* Advanced Error Capability Identifier

 

 

 

 

 

Bits

 

Type

Reset

Description

 

 

 

 

 

31:20

 

RO

300h

Next PCI Express* Extended Capability Pointer: This field points to the PCI Express*

 

Power Budgeting Capability as the next capability.

 

 

 

 

 

 

 

 

 

19:16

 

RO

1h

Advanced Error Capability Version Number: This field indicates the PCI Express*

 

Advanced Error Reporting Extended Capability Version Number.

 

 

 

 

 

 

 

 

 

15:0

 

RO

0001h

Advanced Error Capability ID: This field indicates the PCI Express* Extended Capability

 

ID, indicating Advanced Error Reporting Capability.

 

 

 

 

 

 

 

 

 

12.2.52Offset 104h: ERRUNC_STS—PCI Express* Uncorrectable Error Status Register

This register reports the error status of individual uncorrectable error sources. An individual error status bit that is set to 1 indicates that a particular error occurred. Software can clear an error status by writing a 1 to the respective bit.

Table 86.

Offset 104h: ERRUNC_STS—PCI Express* Uncorrectable Error Status Register

 

 

 

 

 

Bits

 

Type

Reset

Description

 

 

 

 

 

31:21

 

RsvdZ

000h

Reserved Zero: Software must write 0 to these bits.

 

 

 

 

 

20

 

RWCS

0b

Unsupported Request Error Status: This bit is set whenever an unsupported request is

 

detected on PCI Express*.

 

 

 

 

 

 

 

 

 

19

 

RO

0b

ECRC Check: The Intel® 41210 Serial to Parallel PCI Bridge does not do ECRC checking,

 

and this bit is never set.

 

 

 

 

 

 

 

 

 

18

 

RWCS

0b

Malformed TLP: This bit is set when it receives a malformed TLP. Header logging is

 

performed.

 

 

 

 

 

 

 

 

 

17

 

RWCS

0b

Receiver Overflow: This bit is set when the PCI Express* interface unit receive buffers

 

overflow.

 

 

 

 

 

 

 

 

 

 

 

 

 

Unexpected Completion: This bit is set whenever a completion is received with a

16

 

RWCS

0b

requestor ID that does not match side A or side B, or when a completion is received with a

 

 

 

 

matching requestor ID but an unexpected tag field. Header logging is performed.

 

 

 

 

 

15

 

RWCS

0b

Completer Abort: The bridge sets this bit and logs the header associated with the request

 

when the configuration unit signals a completer abort.

 

 

 

 

 

 

 

 

 

14

 

RWCS

0b

Completion Time-out:This bit is set when upstream memory configuration I/O reads do

 

not receive completions within 16–32 ms.

 

 

 

 

 

 

 

 

 

13

 

RWCS

0b

Flow Control Protocol Error Status: This bit is set when a flow control protocol error is

 

detected.

 

 

 

 

 

 

 

 

 

12

 

RWCS

0b

Poisoned TLP Received: This bit is set and the bridge logs the header when a poisoned

 

TLP is received from PCI Express*.

 

 

 

 

 

 

 

 

 

11:5

 

RsvdZ

00h

Reserved Zero: Software must write 0 to these bits.

 

 

 

 

 

4

 

RWCS

0b

Data Link Protocol Error: This bit is set when a data link protocol error is detected.

 

 

 

 

 

3:1

 

RsvdZ

000b

Reserved

 

 

 

 

 

0

 

RWCS

0b

Training Error: The 41210 does not set this bit.

 

 

 

 

 

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

105

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Contents Developer’s Manual Intel 41210 Serial to Parallel PCI BridgeIntel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Date Revision Description Revision HistoryPCI Express* Interface Features PCI-X Interface FeaturesIntroduction1 Power Management SMBus InterfaceJtag On-Die Termination ODT Signal DescriptionAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 ODT SignalsADEVSEL# BDEVSEL# AFRAME# BFRAME# AGNT#50 BGNT#50PCI Express* Interface PCI Express* Interface PinsPERCOMP10 TotalPCI Bus Interface Two Instances PCI Interface Pins Sheet 1ADEVSEL# AIRDY#PCI Interface Pins Sheet 2 PCI Interface Pins 64-Bit Extensions PCI Clock and Reset PinsPCI Bus Interface 64-Bit Extension Two Interfaces Interrupt Interface Two Interfaces Interrupt Interface PinsAINTA# AINTB# AINTC# AINTD#Reset Straps Reset Strap PinsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous PinsNumber Description Voltage PinsThis page Intentionally Left Blank PCI-X Interface PCI Mode Pin/Strap EncodingInitialization PCI-X Initialization PatternTransactions Supported PCI ModePCI Transactions Supported Transaction Encoding1PCI-X Mode Read TransactionsPCI-X Transactions Supported Delayed Configuration TransactionsLock Cycles End Point SourcePCI Transaction Termination DecodingPCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface Attributes PCI-X Protocol Specifics2 4 GB and 4 K Page Crossover Wait StatesSplit Transactions ArbitrationFields Split Completion Abort RegistersBridgeM0 High Priority Group Lpg Low Priority B3173-01 Internal Arbitration SchemeHardware-Controlled Active State Power Management Power ManagementSoftware-Driven PCI-PM 1.1-Compatible Power Management PCI Bus Power ManagementPower-Management Event Signaling Pmetoack This page Intentionally Left Blank PCI-to-PCI Bridge a Configuration Space Addressable Space AccessPCI-to-PCI Bridge B Configuration Space Addressing5PCI Express* Configuration Access Configuration-Space AccessDevice Number Signal Used for Public/Private Secondary PCI DevicesAddressing Type 1 to Type 0 Translation PCI and PCI-X Type 0 Configuration Access from PCI-X InterfaceSMBus Configuration Access I/O Space Access MechanismO Forwarding Memory Space Access Mechanism Memory Forwarding Memory-Mapped I/O WindowVGA Addressing Prefetchable Memory WindowOpaque Memory Window § § Upstream Transaction Ordering Transaction OrderingUpstream Transaction Ordering Row Pass ColumnDownstream Transaction Ordering Relaxed Ordering/No-Snoop SupportDownstream Transaction Ordering Interrupt Support Legacy Interrupt SharingINTx Routing Table Interrupt Binding for Devices behind a Bridge Interrupt Routing for Devices behind a BridgeDevice Number on Secondary BusSystem Management Bus Interface SMBus Address AssignmentsBit Value SMBus Command Encoding SMBus CommandsInternal Command SMBus commandConfiguration Initialization SequenceSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Device Reset Clock and ResetClocking Clock DomainsPERST# Reset Mechanism RSTIN# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank Error Handling PCI Express* ErrorsPCI Errors Termination of Completion Required Transactions Error TypesCompletion-Status Translation for Immediate Terminations PCI-X Termination PCI Express* CompletionPCI-X Split Termination Message PCI Express IndexSuccessful 00h PCI Express* Completion Status PCI Completion Split Termination on PCI Express* InterfacePERST# reset Register Nomenclature and Access AttributesRegister Description Bit Attribute DefinitionsConfiguration Registers Capptr PCI/PCI-X Compatible Configuration region0xFFF 0x300 0x100 0x40 0x00 B3174-02Legacy Configuration Space PCI Express* Extended Configuration Space RegisterByte Offset Offset 04h PCICMD-Command Register Sheet 1 Offset 04h PCICMD-Command RegisterReset Description Offset 00h ID-IdentifiersOffset 06h PSTS-Primary Device Status Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status Sheet 1 TypeOffset 06h PSTS-Primary Device Status Sheet 2 Offset 08h REVID-Revision IDOffset 08h REVID-Revision ID BitsOffset 09h CC-Class Code Offset 0Dh PMLT-Primary Master Latency TimerOffset 0Ch CLS-Cache-Line Size Offset 0Eh HEADTYP-Header TypeOffset 1Bh SMLT-Secondary Master Latency Timer Offset 1Bh SMLT-Secondary Master Latency TimerOffset 18h BNUM-Bus Numbers Offset 18h BNUM-Bus NumbersOffset 1Ch IOBL-I/O Base and Limit Offset 1Ch IOBL-I/O Base and LimitFFFh Support for 16-bit I/O addressing onlyOffset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary StatusOffset 20h MBL-Memory Base and Limit Offset 20h MBL-Memory Base and Limit3120 000h Must be less than this valueOffset 24h PMBL-Prefetchable Memory Base and Limit Bits Type Reset DescriptionOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 34h CAPP-Capabilities List Pointer Offset 3Ch INTR-Interrupt InformationOffset 3Eh BCTRL-Bridge Control Sheet 1 Offset 3Eh BCTRL-Bridge ControlOffset 3Eh BCTRL-Bridge Control Sheet 2 Offset 40h BCNF-Bridge Configuration Register Offset 40h BCNF-Bridge Configuration RegisterPeer Memory Read Enable Pmre Bit Maximum Number of Upstream Delayed TransactionsOffset 43h PCLKC-PCI Clock Control Offset 42h MTT-Multi-Transaction TimerOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 45h EXPNXTP-Next Item PointerDefault Description Offset 46h EXPCAP-PCI Express* CapabilityOffset 46h EXPCAP-PCI Express* Capability Offset 4Ch EXPDCTL-PCI Express* Device Control Register Bit MaxReadRequestSizeBit MaxPayloadSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 50h EXPLCAP-PCI Express* Link Capabilities RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 54h EXPLCTL-PCI Express* Link Control Register Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit LatencyOffset 56h EXPLSTS-PCI Express* Link Status Register Offset 5Ch MSICAPID-PCI Express* MSI Capability IdentifierOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 5Eh MSIMC-PCI Express* MSI Message Control Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 60h MSIMA-PCI Express* MSI Message Address Offset 68h MSIMD-PCI Express* MSI Message DataOffset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management CapabilitiesOffset 70h PMPMCSR-Power Management Control/Status Register Offset 72h PMBSE-Power Management Bridge Support ExtensionsOffset 73h PMDATA-Power Management Data Field Offset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item PointerOffset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization RegisterAdvanced Error Reporting Extended Capability Version Number Power Budgeting Capability as the next capabilityID, indicating Advanced Error Reporting Capability When the configuration unit signals a completer abortOffset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error MaskFlow Control Protocol Error Status Severity Unsupported Request Error Status SeverityData Link Protocol Error Severity Training Error Severity Not supportedOffset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error StatusOffset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error MaskOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Logs the header Sheet 2PCI Delayed Transaction Timer Expiry Mask Internal Bridge Data Error MaskPCI-X Uncorrectable Address Parity Error Detected Mask PCI-X Uncorrectable Attribute Parity Error Detected MaskPCI-X Detected Split Completion Master Abort Mask PCI-X Detected Target Abort Mask optional in specificationPCI Delayed Transaction Timer Expiry Severity Internal Bridge Data Error SeverityPCI-X Uncorrectable Address Parity Error Detected Severity PCI-X Uncorrectable Data Parity Error Detected SeverityRwcs = Errnonfatal = Errfatal PCI-X Detected Split Completion Master Abort SeverityRegister is cleared by the software writing a 1 to the bit Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Type Reset DescriptionOffset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterOffset 170h SSR-Strap Status Register Offset 170h SSR-Strap Status RegisterReserved Read only SMBUS5 SMBUS3 SMBUS2 SMBUS1Offset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data Register
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