Intel IXP1200 Expected Ethernet Transmit Bandwidth, Frame and PDU Length vs. IP Packet Length

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

PDUs because 8-bytes of LLC/SNAP plus 8 bytes of AAL5 trailer push them over the 48 byte payload capacity of a single ATM cell.

Fully populated 64-byte minimum-sized Ethernet frames carry 46-byte IP packets, and also fit into 2 cell PDUs, as do IP packets up through 80 bytes.

Figure 2. Frame and PDU Length vs. IP Packet Length

1.3.3Expected Ethernet Transmit Bandwidth

This example design has more Ethernet transmit wire capacity than most full-bandwidth ATM input workloads is able to consume. All configurations of this example design include more Ethernet bandwidth than ATM bandwidth. This assures that Ethernet reception is fast enough to supply ATM transmit at full wire rate, and that Ethernet can transmit fast enough to consume ATM receive at full wire rate.

When Ethernet receive bandwidth exceeds ATM transmit wire-rate, the design discards the excess Ethernet input. In the reverse direction, ATM receive wire-rate is less than Ethernet transmit wire- rate, and so Ethernet transmit will never be fully consumed.

Given that the design receives cells at OC-3 or OC-12 wire-rate, Figure 3 shows the expected Ethernet Transmit bandwidth. This pattern is a direct result of the minimum Ethernet frame size and cell granularity of AAL5 shown in the previous figure. For example, a 32-byte IP packet would completely fill one cell, and when forwarded to Ethernet, Ethernet it expands to consume the entire 84-bytes of wire-time associated with a 64-byte minimum size Ethernet frame. In this scenario ATM is more Mbps efficient than Ethernet, 949 Mbps Ethernet output would be expected. However, as only 800Mbps of Ethernet bandwidth is available, the one-cell PDU workload will drive the Ethernet wires to their 800Mbps capacity and discard the last 149Mbps.

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Application Note

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Purpose of ATM Example Design IntroductionScope of Example Design Supported / Not Implemented Functions Configuration DescriptionBackground Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box System Programming Model System OverviewHardware StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables ATM to Ethernet Data Flow Data FlowVC Lookup IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowATM Receive Microengine Microengine Functional BlocksMicroengine Initialization StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Receive Structure Ethernet Transmit MicroengineEthernet Receive High Level Algorithm Ethernet Transmit Structure CRC-32 Calculations using IXP1240/1250 HardwareCRC-32 Hardware Checking on Receive Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorCRC-32 Checker and Generator High Level Algorithm Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryBuffer Offset Buffer Index Entry DescriptionCell data11 Entry Description Virtual Circuit Lookup Table Cache VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration VC Cache StructureIP Table Function IP Lookup TableVC Cache API IP Table StructureMtuchange IP Table Management APIRoutetableinit AtmrouteaddRoutedelete EnetrouteaddRtentinfo RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8Next BD Last Quad Queue Index Sram Buffer Descriptor FormatATM Header Entry Description 2 3 4 Dram Data Buffer Format2 3 4 5 6 7 8 Bytes Enet SrcAdrSequencehandle Usage Sequence Numbers sequence.ucSystem Limit on Packet Buffers API Call DescriptionExample Message Queues msgq.ucUsage Model Step Sequence Operation Bakery Line AnalogyMsgqinitregs Msgqhandle ParametersMsgqinitqueue MsgqsendMsgqreceive RamoptionBuffer Descriptor Queues bdq.uc 1.1 FeaturesFeature Description BDQ Management MacrosCounters CountCounter Base Address Global ParametersUse of the Counter Subsystem Counter Index#define Statement Description Global Counter Enable and FlagsCounter Flags Counter Group DescriptionCounterinc Counters.uc CounterresetPortcounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutexvectorenter Mutex VectorsMutexvectorinit MutexvectorexitInter-Thread Signalling Project Configuration / Modifying the Example DesignProjectconfig.h Systemconfig.h Testing EnvironmentsSwitching Between Hardware Configurations Limitations Simulation Support Scripts, etcExtending the Example Design Byte Document ConventionsAcronyms & Definitions 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description