Intel IXP1200 manual Vctablehashed Structure

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

The OC-12 configuration uses a VC Table Cache in conjunction with the VC table, however the description of the backing VC table in this section applies with or without the presence of a VC Cache.

The VC table entry answers the following questions for the ATM Receive thread:

•Is the VC open? (If no, discard the cell)

•Which LLC/SNAP patterns are expected at the start of each PDU? (If no match, discard cell.)

•Which AAL is the VC open for? (ATM Receive currently processes only AAL5.)

•Where should ATM Receive put the payload in DRAM (buffer and offset)?

•For hardware CRC: what is the current syndrome for this PDU?

4.1.2VC_TABLE_HASHED Structure

VC_TABLE_HASHED supports the entire ATM VC name-space by employing the IXP12xx hashing hardware as follows:

•At initialization, microcode loads the hash48 multiplier CSRs with the largest prime number that fits into 48 bits: 0xffffffffffc5.

•At run-time, ATM Receive locates entries like so:

key = (atm_header & 0xFFFFFFF0) port#) hash_output = hash1_48[key]

Index = ((hash_output) ^ (hash_output >> 16) ^ (hash_output >> 32)) & 0xFFFF

The index is used to read an entry from a 64K entry "primary" hashed VC Table in SRAM. If the key in the entry matches the starting key, the hash table has successfully delivered the right VC table entry with just one SRAM read. If the key does not match the key in the entry read from the primary table, it follows a linked "collision" list threaded with the entry "Next" field (see figure Figure 23)

30	Application Note

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Supported / Not Implemented Functions Configuration DescriptionBackground Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowATM Receive Microengine Microengine Functional BlocksMicroengine Initialization StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorCRC-32 Checker and Generator High Level Algorithm Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryEntry Description Buffer Offset Buffer IndexCell data11 Entry Description Virtual Circuit Lookup Table Cache VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration VC Cache StructureIP Table Function IP Lookup TableVC Cache API IP Table StructureMtuchange IP Table Management APIRoutetableinit AtmrouteaddRoutedelete EnetrouteaddRtentinfo RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8Sram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description 2 3 4 Dram Data Buffer Format2 3 4 5 6 7 8 Bytes Enet SrcAdrSequencehandle Usage Sequence Numbers sequence.ucSystem Limit on Packet Buffers API Call DescriptionExample Message Queues msgq.ucUsage Model Step Sequence Operation Bakery Line AnalogyMsgqinitregs Msgqhandle ParametersMsgqinitqueue MsgqsendMsgqreceive RamoptionBuffer Descriptor Queues bdq.uc 1.1 FeaturesFeature Description BDQ Management MacrosCounters CountCounter Base Address Global ParametersUse of the Counter Subsystem Counter Index#define Statement Description Global Counter Enable and FlagsCounter Flags Counter Group DescriptionCounters.uc Counterreset CounterincPortcounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutexvectorenter Mutex VectorsMutexvectorinit MutexvectorexitProject Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design Byte Document ConventionsAcronyms & Definitions 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description