Intel IXP1200 manual ATM to Ethernet Data Flow, VC Lookup

Page 17

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

Figure 9. IXP1200 2xATM OC-3 Software-CRC and 4xEthernet 100Mbps Microengine Partitioning

ATM RX

OC-3	Port 8
OC-3	Port 9	*
	Port 9	*
	IP Route
	IP Route	MSGQ

CRC CHK

Check

Check

Check

Check

PktQ

PktQ

PktQ

PktQ

Ethernet TX

Scheduler

Fill

Fill

Fill

Ethernet

Ethernet

Ethernet

Ethernet

ATM TX

OC-3	Port 8	BDQ
OC-3	Port 9	BDQ
	Unused
	Unused
Legend:

CRC GEN

Generate

Generate

Generate

Generate

MSGQ

Ethernet RX
Port0	Ethernet
Port1	Ethernet
Port2	Ethernet
Port3	Ethernet

= Thread		=	Scratchpad
= Microengine			Memory	= MSGQ
= Physical Port		=	SRAM

A9636-01

2.4Data Flow

2.4.1ATM to Ethernet Data Flow

Figure 10 outlines the processing to receive ATM cells and forward them to Ethernet ports. For a given VC, three different types of cells of the PDU can arrive: the first cell, middle cells, and last cell:

1.The first cell of the IP over ATM PDU contains three types of headers: ATM header, LLC/ SNAP header, and IP Header. This is sufficient information to make a forwarding decision. The payload portion of this cell is moved directly from the RFIFO to DRAM.

2.Subsequent middle cells are moved directly from the RFIFO to DRAM without any additional processing.

3.When the last cell of the PDU (which contains the AAL5 trailer) is received, the payload of the cell is moved directly from the RFIFO to DRAM, and the completed PDU is then enqueued for Ethernet transmission.

2.4.1.1VC Lookup

A VC lookup is performed on each cell received over an ATM port. The appropriate VC Table Entry is located using the VPI/VCI value in the ATM header plus the port number. The lookup provides an DRAM packet buffer base address, plus the CRC-32 syndrome for the PDU. As each additional payload is added to the DRAM buffer, the offset value is incremented and the CRC

Application Note

17

Modified on: 3/20/02,

Image 17

Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Scope of Example Design IntroductionPurpose of ATM Example Design Background Configuration DescriptionSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box Hardware System OverviewSystem Programming Model System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables VC Lookup Data FlowATM to Ethernet Data Flow ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationMicroengine Initialization Microengine Functional BlocksATM Receive Microengine StructureOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Receive High Level Algorithm Ethernet Transmit MicroengineEthernet Receive Structure CRC-32 Hardware Checking on Receive CRC-32 Calculations using IXP1240/1250 HardwareEthernet Transmit Structure First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCVirtual Circuit Lookup Table atmvctable.uc Software Subsystems & Data StructuresCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cCell data11 Entry Description Entry DescriptionBuffer Offset Buffer Index 1.2 OC-3 Configuration VC Cache Function 1.1 OC-12 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureVC Cache API IP Lookup TableIP Table Function IP Table StructureRoutetableinit IP Table Management APIMtuchange AtmrouteaddRtentinfo EnetrouteaddRoutedelete Rthelp2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersATM Header Entry Description Sram Buffer Descriptor FormatNext BD Last Quad Queue Index 2 3 4 5 6 7 8 Bytes Dram Data Buffer Format2 3 4 Enet SrcAdrSystem Limit on Packet Buffers Sequence Numbers sequence.ucSequencehandle Usage API Call DescriptionUsage Model Message Queues msgq.ucExample Step Sequence Operation Bakery Line AnalogyMsgqinitqueue Msgqhandle ParametersMsgqinitregs MsgqsendRamoption MsgqreceiveFeature Description 1.1 FeaturesBuffer Descriptor Queues bdq.uc BDQ Management MacrosCount CountersUse of the Counter Subsystem Global ParametersCounter Base Address Counter IndexCounter Flags Global Counter Enable and Flags#define Statement Description Counter Group DescriptionPortcounterinc Counters.uc CounterresetCounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorinit Mutex VectorsMutexvectorenter MutexvectorexitProjectconfig.h Project Configuration / Modifying the Example DesignInter-Thread Signalling Switching Between Hardware Configurations Testing EnvironmentsSystemconfig.h Extending the Example Design Simulation Support Scripts, etcLimitations Acronyms & Definitions Document ConventionsByte 10 11 12 13 14 15 16 ... BytesTitle Description Related Documents