Intel IXP1200 manual Introduction, Purpose of ATM Example Design, Scope of Example Design

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

1.0Introduction

Intel develops example software to demonstrate the capabilities of the IXP1200 Network Processor Family. This document describes the implementation of example software demonstrating the IXP1200, IXP1240, and IXP1250 in an ATM environment. In particular, this example design uses the IXP12xx to route IP packets between ATM and Ethernet networks.

From the point of view of this example software, the IXP1240 and IXP1250 are synonymous - the project utilizes their common hardware CRC feature; but is not aware of the IXP1250’s additional ECC capability. The IXP1200, on the other hand, does not have hardware CRC support, and thus supports only a software-CRC configuration.

This document serves as a companion to the comments in the source code, and is intended to clarify the structure and general workings of the design. The following material is covered: purpose and scope of the design; software partitioning and data flow, StrongARM® Core and microengine initialization; microengine functional block description; subsystems and data structures; inter- thread signaling; project configuration; testing environments; simulation support; limitations, and example design extension. The end of this document contains lists of document conventions, acronyms and definitions, and related documents.

1.1Purpose of ATM Example Design

This example design demonstrates just one software architecture in which the IXP12xx can be used in ATM-related designs. It is not intended to be ’production ready’. Rather, it is intended to serve as a starting point for customers designing similar applications. It is also intended for customers to understand the IXP12xx Network Processor’s capabilities and expected performance.

Users may modify the code, adding additional modules that are proprietary or more specific to their needs, and estimate performance, although performance numbers gained from this design are applicable only to the example as presented. Customer changes to the design can result in either increases or decreases in performance.

1.2Scope of Example Design

This document describes the implementation in sufficient detail that a programmer should be able to successfully modify the source code. The README.txt file that accompanies the software should be consulted for instructions on running the project, building the code, and the actual layout of the source files.

Application Note

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Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Purpose of ATM Example Design IntroductionScope of Example Design Ethernet, IP and AAL5 Protocol Processing Configuration DescriptionBackground Supported / Not Implemented FunctionsSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box System Programming Model System OverviewHardware System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables ATM to Ethernet Data Flow Data FlowVC Lookup ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationStructure Microengine Functional BlocksMicroengine Initialization ATM Receive MicroengineOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Receive Structure Ethernet Transmit MicroengineEthernet Receive High Level Algorithm Ethernet Transmit Structure CRC-32 Calculations using IXP1240/1250 HardwareCRC-32 Hardware Checking on Receive First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCCRC-32 Computation Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 Checker and Generator High Level AlgorithmVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cBuffer Offset Buffer Index Entry DescriptionCell data11 Entry Description VC Cache Structure VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration Virtual Circuit Lookup Table CacheIP Table Structure IP Lookup TableVC Cache API IP Table FunctionAtmrouteadd IP Table Management APIRoutetableinit MtuchangeRthelp EnetrouteaddRtentinfo Routedelete2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersNext BD Last Quad Queue Index Sram Buffer Descriptor FormatATM Header Entry Description Enet SrcAdr Dram Data Buffer Format2 3 4 5 6 7 8 Bytes 2 3 4API Call Description Sequence Numbers sequence.ucSystem Limit on Packet Buffers Sequencehandle UsageStep Sequence Operation Bakery Line Analogy Message Queues msgq.ucUsage Model ExampleMsgqsend Msgqhandle ParametersMsgqinitqueue MsgqinitregsRamoption MsgqreceiveBDQ Management Macros 1.1 FeaturesFeature Description Buffer Descriptor Queues bdq.ucCount CountersCounter Index Global ParametersUse of the Counter Subsystem Counter Base AddressCounter Group Description Global Counter Enable and FlagsCounter Flags #define Statement DescriptionCounterinc Counters.uc CounterresetPortcounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorexit Mutex VectorsMutexvectorinit MutexvectorenterInter-Thread Signalling Project Configuration / Modifying the Example DesignProjectconfig.h Systemconfig.h Testing EnvironmentsSwitching Between Hardware Configurations Limitations Simulation Support Scripts, etcExtending the Example Design 10 11 12 13 14 15 16 ... Bytes Document ConventionsAcronyms & Definitions ByteTitle Description Related Documents
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