Intel IXP1200 manual Portcounterinc Algorithm, Intotaldiscards

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

Parameter	Description

IN_TOTAL_DISCARDS	Address of global discard counter.

	Highest valid port number -- from a per-port counters point of view.
	If the sum of IN_PORT_BASE and in_port_index exceeds
IN_MAX_PORT_NUMBER	IN_MAX_PORT_NUMBER, then the port number is truncated to
IN_MAX_PORT_NUMBER	IN_MAX_PORT_NUMBER. This allows limiting the scratchpad
	RAM dedicated to counters while still allowing event counting on
	very high numbered ports (e.g., logical ports used by the
	StrongARM core)

	Counter increment flag. Must match the
	COUNTERS_ENABLE_MASK bit. If set to
IN_ENABLE_FLAGS	COUNT_PORT_EXCEPTIONS, the global counter at
	IN_TOTAL_DISCARDS will be incremented in addition to the per-
	port counter.

port_counter_inc() Algorithm

#if (IN_ENABLE_FLAGS & COUNTERS_ENABLE_MASK)

addr = IN_PORT_COUNTERS_BASE + 16 * (IN_PORT_BASE + in_port_index) +

IN_EXCEPTION_INDEX *addr += 1

#endif

#if (IN_ENABLE_FLAGS & COUNT_PORT_EXCEPTIONS) IN_TOTAL_DISCARDS += 1

#endif

Example

#define COUNT_PORT_EVENTS (1 << 11) // normal port activity #define COUNT_PORT_EXCEPTIONS (1 << 12) // per-port exceptions

The 16 per-port counters are named by various include files, as summarized by the string table that counters_print() uses to print the per-port counters:

char *port_counter_strings [] = { "PORT_FULLQ",//0x00 port.uc "PORT_RXERROR", //0x01 port.uc "PORT_RXFAIL",//0x02 port.uc "port counter 3", "PORT_RXCANCEL",//0x04 port.uc "PORT_SHDBE_SOP",//0x05 port.uc "PORT_SHDBE_NOT_SOP", //0x06 port.uc "port counter 7", "IP_BAD_TOTAL_LENGTH", //0x08 ip.uc "IP_BAD_TTL", //0x09 ip.uc "IP_BAD_CHECKSUM", //0x0a ip.uc "IP_NO_ROUTE", //0x0b ip.uc "IP_INVALID_ADDRESS", //0x0c ip.uc "MAC_INVALID_ADDRESS", //0x0d ether.uc "IP_DBCAST_ADDRESS", //0x0e ip.uc "PORT_DISABLED", //0x0f ip.uc

#define PORT_EXCEPTION EXCEPTION_COUNTERS, TOTAL_DISCARDS, ATM_PORT3,

COUNT_PORT_EXCEPTIONS

port_counter_inc(port_idx, ATM_PORT0, PORT_FULLQ, PORT_EXCEPTION)

50	Application Note

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Scope of Example Design IntroductionPurpose of ATM Example Design Supported / Not Implemented Functions Configuration DescriptionBackground Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box Hardware System OverviewSystem Programming Model StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables VC Lookup Data FlowATM to Ethernet Data Flow IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowATM Receive Microengine Microengine Functional BlocksMicroengine Initialization StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Receive High Level Algorithm Ethernet Transmit MicroengineEthernet Receive Structure CRC-32 Hardware Checking on Receive CRC-32 Calculations using IXP1240/1250 HardwareEthernet Transmit Structure Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorCRC-32 Checker and Generator High Level Algorithm Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryCell data11 Entry Description Entry DescriptionBuffer Offset Buffer Index Virtual Circuit Lookup Table Cache VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration VC Cache StructureIP Table Function IP Lookup TableVC Cache API IP Table StructureMtuchange IP Table Management APIRoutetableinit AtmrouteaddRoutedelete EnetrouteaddRtentinfo RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8ATM Header Entry Description Sram Buffer Descriptor FormatNext BD Last Quad Queue Index 2 3 4 Dram Data Buffer Format2 3 4 5 6 7 8 Bytes Enet SrcAdrSequencehandle Usage Sequence Numbers sequence.ucSystem Limit on Packet Buffers API Call DescriptionExample Message Queues msgq.ucUsage Model Step Sequence Operation Bakery Line AnalogyMsgqinitregs Msgqhandle ParametersMsgqinitqueue MsgqsendMsgqreceive RamoptionBuffer Descriptor Queues bdq.uc 1.1 FeaturesFeature Description BDQ Management MacrosCounters CountCounter Base Address Global ParametersUse of the Counter Subsystem Counter Index#define Statement Description Global Counter Enable and FlagsCounter Flags Counter Group DescriptionPortcounterinc Counters.uc CounterresetCounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutexvectorenter Mutex VectorsMutexvectorinit MutexvectorexitProjectconfig.h Project Configuration / Modifying the Example DesignInter-Thread Signalling Switching Between Hardware Configurations Testing EnvironmentsSystemconfig.h Extending the Example Design Simulation Support Scripts, etcLimitations Byte Document ConventionsAcronyms & Definitions 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description