Intel IXP1200 Software Subsystems & Data Structures, Virtual Circuit Lookup Table atmvctable.uc

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

3.7.2CRC-32 Checker and Generator High Level Algorithm

Figure 20. CRC-32 High Level Algorithm

// CRC Checker

while(1)

dequeue PDU from CRC CHK BDQ calculate_crc() over entire PDU

if (AAL5 trailer CRC == calculated CRC)

enqueue PDU onto Ethernet Transmit packet queue else

drop PDU endif

//CRC Generator

while(1)

dequeue PDU from CRC GEN BDQ calculate_crc() over entire PDU

write calculated CRC into AAL5 trailer in DRAM data buffer enqueue PDU onto ATM TX UBR BDQ

The PDUs within each VC on each port are enqueued on the output in the same order that they were dequeued from the input.

3.7.3CRC-32 Computation

CRC-32 computation is performed by the calculate_crc32() macro in atm_aal5_crc32lib.uc.

The data stream is used to index tables of pre-computed CRC-32 results. The results are combined serially to produce the CRC-32 for the entire AAL5 PDU.

The lookup tables are generated by code in atm_aal5_crc32_table.c. In simulation, the code produces files that contain the tables and are downloaded into SRAM by startup scripts.

For hardware, the tables are generated by the same code running on the StrongARM core, but rather than creating files, the tables are written directly to memory.

4.0Software Subsystems & Data Structures

4.1Virtual Circuit Lookup Table - atm_vc_table.uc

4.1.1VC Table Function

The ATM receive microengine uses a VC Lookup Table to manage reassembly of cells into PDUs. The virtual circuit address bits in each cell header, plus the receive port number, uniquely specify a VC table entry for that VC. ATM Receive performs a VC Lookup to qualify every cell received.

The lookup returns the VC Lookup Table Entry structure with the format shown in Figure 23 and Figure 24.

Application Note

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Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Scope of Example Design IntroductionPurpose of ATM Example Design Background Configuration DescriptionSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box Hardware System OverviewSystem Programming Model System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables VC Lookup Data FlowATM to Ethernet Data Flow ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationMicroengine Initialization Microengine Functional BlocksATM Receive Microengine StructureOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Receive High Level Algorithm Ethernet Transmit MicroengineEthernet Receive Structure CRC-32 Hardware Checking on Receive CRC-32 Calculations using IXP1240/1250 HardwareEthernet Transmit Structure First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCVirtual Circuit Lookup Table atmvctable.uc Software Subsystems & Data StructuresCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cCell data11 Entry Description Entry DescriptionBuffer Offset Buffer Index 1.2 OC-3 Configuration VC Cache Function 1.1 OC-12 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureVC Cache API IP Lookup TableIP Table Function IP Table StructureRoutetableinit IP Table Management APIMtuchange AtmrouteaddRtentinfo EnetrouteaddRoutedelete Rthelp2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersATM Header Entry Description Sram Buffer Descriptor FormatNext BD Last Quad Queue Index 2 3 4 5 6 7 8 Bytes Dram Data Buffer Format2 3 4 Enet SrcAdrSystem Limit on Packet Buffers Sequence Numbers sequence.ucSequencehandle Usage API Call DescriptionUsage Model Message Queues msgq.ucExample Step Sequence Operation Bakery Line AnalogyMsgqinitqueue Msgqhandle ParametersMsgqinitregs MsgqsendRamoption MsgqreceiveFeature Description 1.1 FeaturesBuffer Descriptor Queues bdq.uc BDQ Management MacrosCount CountersUse of the Counter Subsystem Global ParametersCounter Base Address Counter IndexCounter Flags Global Counter Enable and Flags#define Statement Description Counter Group DescriptionPortcounterinc Counters.uc CounterresetCounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorinit Mutex VectorsMutexvectorenter MutexvectorexitProjectconfig.h Project Configuration / Modifying the Example DesignInter-Thread Signalling Switching Between Hardware Configurations Testing EnvironmentsSystemconfig.h Extending the Example Design Simulation Support Scripts, etcLimitations Acronyms & Definitions Document ConventionsByte 10 11 12 13 14 15 16 ... BytesTitle Description Related Documents