Intel IXP1200 manual VC Table Management API atmutils.c, VC Table Entry

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

Figure 22. VC Table Index

bit positions:

Z

Y

X

-

Port

VPI

VCI

Bit Position

Description

XVCI_SIGNIFICANT_BITS - 1

YVCI_SIGNIFICANT_BITS + VPI_SIGNIFICANT_BITS - 1

ZVCI_SIGNIFICANT_BITS + VPI_SIGNIFICANT_BITS + PORT_SIGNIFICANT_BITS - 1

The project defaults to support a 64K-entry VC table - independent of the number of ports. It does this with eight significant VCI bits, and eight more bits split between VPI and ports. This means that the design can distinguish the difference between 64K different VCs. However, it does not mean that the design can simultaneously reassemble PDUs on all 64K entries. The system supports only 16K packet buffers, and would run out of buffers were it to attempt to assemble PDUs on more than 16K VCs.

4.1.4VC Table Management API - atm_utils.c

atm_utils.c implements C-language utilities to manage the VC Lookup Table. These utilities are available both in simulation at the Transactor command prompt, as well as VxWorks kernel entry points.

The current implementation assumes Permanent Virtual Circuits (PVCs), i.e. it does not support the StrongARM core updating the VC table while the microcode is using the table. Switched Virtual Circuit (SVC) support could be added by employing SRAM locks or atomic operations to avoid conflicts between simultaneous StrongARM core and microengine access to the same VC entry.

4.1.5VC Table Entry

The format of the VC Table entry for VC_TABLE_HASHED is the same as for

VC_TABLE_LINEAR, with the addition of 2 32-bit words to hold the Next address and the hash Key for the entry.

This format is only partially hidden from ATM Receive, the consumer of the VC table API, though macros could be implemented to make it appear to opaque.

Figure 23. VC Lookup Entry Table (VC_TABLE_HASHED)

3

3

2

2

2

2

2

2

2

2

2

2

1

1

1

1

1

1

1

1

1

1

9

8

7

6

5

4

3

2

1

0

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Buffer Offset

 

 

 

 

 

 

 

 

Buffer Index

 

 

 

 

 

 

LLC/SNAP

Q

 

AAL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Cell data11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

Application Note

Modified on: 3/20/02,

Page 31 Page 33
Image 32
Page 31 Page 33
Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Scope of Example Design IntroductionPurpose of ATM Example Design Configuration Description BackgroundSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box Hardware System OverviewSystem Programming Model StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables VC Lookup Data FlowATM to Ethernet Data Flow IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowMicroengine Functional Blocks Microengine InitializationATM Receive Microengine StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Receive High Level Algorithm Ethernet Transmit MicroengineEthernet Receive Structure CRC-32 Hardware Checking on Receive CRC-32 Calculations using IXP1240/1250 HardwareEthernet Transmit Structure Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorSoftware Subsystems & Data Structures Virtual Circuit Lookup Table atmvctable.ucCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryCell data11 Entry Description Entry DescriptionBuffer Offset Buffer Index VC Cache Function 1.1 OC-12 Configuration 1.2 OC-3 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureIP Lookup Table VC Cache APIIP Table Function IP Table StructureIP Table Management API RoutetableinitMtuchange AtmrouteaddEnetrouteadd RtentinfoRoutedelete RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8ATM Header Entry Description Sram Buffer Descriptor FormatNext BD Last Quad Queue Index Dram Data Buffer Format 2 3 4 5 6 7 8 Bytes2 3 4 Enet SrcAdrSequence Numbers sequence.uc System Limit on Packet BuffersSequencehandle Usage API Call DescriptionMessage Queues msgq.uc Usage ModelExample Step Sequence Operation Bakery Line AnalogyMsgqhandle Parameters MsgqinitqueueMsgqinitregs MsgqsendMsgqreceive Ramoption1.1 Features Feature DescriptionBuffer Descriptor Queues bdq.uc BDQ Management MacrosCounters CountGlobal Parameters Use of the Counter SubsystemCounter Base Address Counter IndexGlobal Counter Enable and Flags Counter Flags#define Statement Description Counter Group DescriptionPortcounterinc Counters.uc CounterresetCounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutex Vectors MutexvectorinitMutexvectorenter MutexvectorexitProjectconfig.h Project Configuration / Modifying the Example DesignInter-Thread Signalling Switching Between Hardware Configurations Testing EnvironmentsSystemconfig.h Extending the Example Design Simulation Support Scripts, etcLimitations Document Conventions Acronyms & DefinitionsByte 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description
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