Intel IXP1200 manual Msgqhandle Parameters, Msgqinitqueue, Msgqinitregs, Msgqsend

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

4.6.1MSGQ_HANDLE Parameters

The following parameters make up MSGQ_HANDLE and are common to all macros in msgq.uc:

Parameter

Description

 

 

 

GPR storing the current index into the queue. An absolute register is used to share the

io_index

index between threads. However, if the threads don’t share access to the queue, a relative

 

GPR can be used.

 

 

in_base_addr

GPR storing the base address of the queue in RAM_TYPE (scratchpad or SRAM). An

absolute GPR is used when the queue is shared between threads.

 

 

 

in_const_one

The value one in a GPR, typically absolute, or the constant 1. The register is generally

used to save cycles.

 

 

 

BASE_ADDR

Base address of the queue in RAM_TYPE -- loaded into in_base_addr by msgq_init().

 

 

 

Synchronization type, as follows:

 

#define MSGQ_ASYNC 0 - return immediately, with or without data

SYNC_TYPE

#define MSGQ_SYNC_POLL 1 - wait for data -- poll while waiting

 

#define MSGQ_SYNC_SLEEP 2 - wait for data -- sleep while waiting, sender must know

 

to wake up receiver

 

 

RAM_TYPE

RAM type. Typically scratchpad, can also be SRAM.

 

 

MSGQ_SIZE

Number of longwords in the message queue. Must be a power of 2. 16 is typically used for

scratchpad queues because it saves instructions.

 

 

 

4.6.2msgq_init_queue()

Initializes the global queue in RAM_TYPE. Called by central initialization code before queues are accessed.

msgq_init_queue(MSGQ_HANDLE)

Parameter

Description

 

 

MSGQ_HANDLE

Parameters described in “MSGQ_HANDLE Parameters”.

 

 

4.6.3msgq_init_regs()

Initializes the registers used to access the queue. Called by both producer and consumer.

msgq_init_regs(MSGQ_HANDLE)

Parameter

Description

 

 

MSGQ_HANDLE

Parameters described in “MSGQ_HANDLE Parameters”.

 

 

4.6.4msgq_send()

Sends a message to the queue.

Application Note

43

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Purpose of ATM Example Design IntroductionScope of Example Design Ethernet, IP and AAL5 Protocol Processing Configuration DescriptionBackground Supported / Not Implemented FunctionsSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box System Programming Model System OverviewHardware System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables ATM to Ethernet Data Flow Data FlowVC Lookup ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationStructure Microengine Functional BlocksMicroengine Initialization ATM Receive MicroengineOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Receive Structure Ethernet Transmit MicroengineEthernet Receive High Level Algorithm Ethernet Transmit Structure CRC-32 Calculations using IXP1240/1250 HardwareCRC-32 Hardware Checking on Receive First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCCRC-32 Computation Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 Checker and Generator High Level AlgorithmVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cBuffer Offset Buffer Index Entry DescriptionCell data11 Entry Description VC Cache Structure VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration Virtual Circuit Lookup Table CacheIP Table Structure IP Lookup TableVC Cache API IP Table FunctionAtmrouteadd IP Table Management APIRoutetableinit MtuchangeRthelp EnetrouteaddRtentinfo Routedelete2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersNext BD Last Quad Queue Index Sram Buffer Descriptor FormatATM Header Entry Description Enet SrcAdr Dram Data Buffer Format2 3 4 5 6 7 8 Bytes 2 3 4API Call Description Sequence Numbers sequence.ucSystem Limit on Packet Buffers Sequencehandle UsageStep Sequence Operation Bakery Line Analogy Message Queues msgq.ucUsage Model ExampleMsgqsend Msgqhandle ParametersMsgqinitqueue MsgqinitregsRamoption MsgqreceiveBDQ Management Macros 1.1 FeaturesFeature Description Buffer Descriptor Queues bdq.ucCount CountersCounter Index Global ParametersUse of the Counter Subsystem Counter Base AddressCounter Group Description Global Counter Enable and FlagsCounter Flags #define Statement DescriptionCounterinc Counters.uc CounterresetPortcounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorexit Mutex VectorsMutexvectorinit MutexvectorenterInter-Thread Signalling Project Configuration / Modifying the Example DesignProjectconfig.h Systemconfig.h Testing EnvironmentsSwitching Between Hardware Configurations Limitations Simulation Support Scripts, etcExtending the Example Design 10 11 12 13 14 15 16 ... Bytes Document ConventionsAcronyms & Definitions ByteTitle Description Related Documents