Intel IXP1200 Testing Environments, Systemconfig.h, Switching Between Hardware Configurations

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

//Define DEBUG to enable all the counters and run-time checking.

//Disable for maximum performance.

//#define DEBUG

//Define COUNTERS_ENABLE_MASK to all 1’s to enable every system counter.

//Otherwise its default is set in system_config.h

//#define COUNTERS_ENABLE_MASK0xFFFFFFFF

//Define ATM_LOOPBACK to allow hardware configurations with ATM outputs

//connected directly to ATM inputs -- either via board loopback jumper

//or external loopback cable. Normally the design would discard

//an IP packet received on ATM with an IP destination on an ATM port.

//ATM_LOOPBACK simply forwards it to the next ethernet port.

#define ATM_LOOPBACK

//Define ETHERNET_LOOPBACK to allow routing packets from Ethernet

//Receive to Ethernet Transmit. Otherwise packets received on

//Ethernet ports with Ethernet destinations will be discarded.

//Useful for equipment check-out in the lab.

//#define ETHERNET_LOOPBACK

//Define RFC1812 to enable all the required router tests under spec RFC1812

//on ethernet to ethernet and ATM to ethernet traffic.

#define RFC1812

5.2system_config.h

The system_config.h header file is used to define ATM headers, counters, and other settings. The project’s README.txt file should be consulted for more detail.

5.3Switching Between Hardware Configurations

As detailed in the README.txt file, the project source code comes with three sub-projects, one for each of the configurations shown above. All of the project source code is shared by the three projects, except for the three files that are necessary to distinguish the hardware configurations - atm_ether.dwp, atm_ether.dwo, and project_config.h. Additional projects can be built from the same source tree by simply copying and modifying the closest sub-project and its three unique files.

The software-CRC configuration can run on any version of the IXP12xx hardware. However, the hardware-CRC configurations depend on the IXP1240 or greater (CHIP_ID >= 6). OC-3 and OC- 12 configurations require different versions of the WAN daughter card (the OC-12 requires a modified OC-3 daughter card).

6.0Testing Environments

In simulation, this project was tested with IXA SDK V2.01 Development Environment on Windows 2000. On hardware, it has been tested with VxWorks Tornado 2.1, on the IXDP1240 Advanced Development Platform.

Application Note

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Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Purpose of ATM Example Design IntroductionScope of Example Design Ethernet, IP and AAL5 Protocol Processing Configuration DescriptionBackground Supported / Not Implemented FunctionsSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box System Programming Model System OverviewHardware System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables ATM to Ethernet Data Flow Data FlowVC Lookup ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationStructure Microengine Functional BlocksMicroengine Initialization ATM Receive MicroengineOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Receive Structure Ethernet Transmit MicroengineEthernet Receive High Level Algorithm Ethernet Transmit Structure CRC-32 Calculations using IXP1240/1250 HardwareCRC-32 Hardware Checking on Receive First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCCRC-32 Computation Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 Checker and Generator High Level AlgorithmVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cBuffer Offset Buffer Index Entry DescriptionCell data11 Entry Description VC Cache Structure VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration Virtual Circuit Lookup Table CacheIP Table Structure IP Lookup TableVC Cache API IP Table FunctionAtmrouteadd IP Table Management APIRoutetableinit MtuchangeRthelp EnetrouteaddRtentinfo Routedelete2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersNext BD Last Quad Queue Index Sram Buffer Descriptor FormatATM Header Entry Description Enet SrcAdr Dram Data Buffer Format2 3 4 5 6 7 8 Bytes 2 3 4API Call Description Sequence Numbers sequence.ucSystem Limit on Packet Buffers Sequencehandle UsageStep Sequence Operation Bakery Line Analogy Message Queues msgq.ucUsage Model ExampleMsgqsend Msgqhandle ParametersMsgqinitqueue MsgqinitregsRamoption MsgqreceiveBDQ Management Macros 1.1 FeaturesFeature Description Buffer Descriptor Queues bdq.ucCount CountersCounter Index Global ParametersUse of the Counter Subsystem Counter Base AddressCounter Group Description Global Counter Enable and FlagsCounter Flags #define Statement DescriptionCounterinc Counters.uc CounterresetPortcounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorexit Mutex VectorsMutexvectorinit MutexvectorenterInter-Thread Signalling Project Configuration / Modifying the Example DesignProjectconfig.h Systemconfig.h Testing EnvironmentsSwitching Between Hardware Configurations Limitations Simulation Support Scripts, etcExtending the Example Design 10 11 12 13 14 15 16 ... Bytes Document ConventionsAcronyms & Definitions ByteTitle Description Related Documents
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