Intel IXP1200 manual Global Parameters, Use of the Counter Subsystem, Counter Base Address

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

On hardware, counters.c is compiled into the atm_utils.o VxWorks-loadable module to provide counters at the VxWorks console.

4.8.1Global Parameters

Parameter

Description

 

 

COUNTERS_BASE

Base address of the scratchpad counter array (mandatory)

 

 

COUNTER_LOCATIONS

Size of the counter array (optional). Default is 64

 

 

COUNTER_STRINGn

String to print for counter n, where n is from 0 until

COUNTER_LOCATIONS -1 (optional). Default is "Counter n"

 

 

 

4.8.2Use of the Counter Subsystem

In this design, system_config.h controls the counter subsystem and defines a handle for each counter. This handle provides the parameters to counter_inc() in the microcode. For example, counter_inc(ATM_RX_CELL_DROP_VC_CLOSED) is invoked in ATM Receive threads every time a cell is discarded because it arrived on a VC that is not open.

#define ATM_RX_CELL_DROP_VC_CLOSED COUNTERS_BASE, 5, COUNT_CELL_DROP

The counter handle has three members:

The base address of the counter array.

The index of the counter in the array.

The flags to determine at compile-time if the counter should be invoked.

4.8.2.1Counter Base Address

The base address of the counter array is defined so that it starts immediately after the per-port exception counters defined in mem_map.h, and it is used as the first member of every counter handle. (This is why the counter example in “counters_print()”starts at (decimal) scratchpad location 195.)

#define COUNTERS_BASE 0xc3

4.8.2.2Counter Index

The index of the counter is simply entered directly into the list of counter handle definitions. Be careful not to duplicate any counter indexes, because it would cause multiple handles to increment the same location.

Application Note

47

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Scope of Example Design IntroductionPurpose of ATM Example Design Ethernet, IP and AAL5 Protocol Processing Configuration DescriptionBackground Supported / Not Implemented FunctionsSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box Hardware System OverviewSystem Programming Model System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables VC Lookup Data FlowATM to Ethernet Data Flow ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationStructure Microengine Functional BlocksMicroengine Initialization ATM Receive MicroengineOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Receive High Level Algorithm Ethernet Transmit MicroengineEthernet Receive Structure CRC-32 Hardware Checking on Receive CRC-32 Calculations using IXP1240/1250 HardwareEthernet Transmit Structure First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCCRC-32 Computation Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 Checker and Generator High Level AlgorithmVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cCell data11 Entry Description Entry DescriptionBuffer Offset Buffer Index VC Cache Structure VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration Virtual Circuit Lookup Table CacheIP Table Structure IP Lookup TableVC Cache API IP Table FunctionAtmrouteadd IP Table Management APIRoutetableinit MtuchangeRthelp EnetrouteaddRtentinfo Routedelete2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersATM Header Entry Description Sram Buffer Descriptor FormatNext BD Last Quad Queue Index Enet SrcAdr Dram Data Buffer Format2 3 4 5 6 7 8 Bytes 2 3 4API Call Description Sequence Numbers sequence.ucSystem Limit on Packet Buffers Sequencehandle UsageStep Sequence Operation Bakery Line Analogy Message Queues msgq.ucUsage Model ExampleMsgqsend Msgqhandle ParametersMsgqinitqueue MsgqinitregsRamoption MsgqreceiveBDQ Management Macros 1.1 FeaturesFeature Description Buffer Descriptor Queues bdq.ucCount CountersCounter Index Global ParametersUse of the Counter Subsystem Counter Base AddressCounter Group Description Global Counter Enable and FlagsCounter Flags #define Statement DescriptionPortcounterinc Counters.uc CounterresetCounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorexit Mutex VectorsMutexvectorinit MutexvectorenterProjectconfig.h Project Configuration / Modifying the Example DesignInter-Thread Signalling Switching Between Hardware Configurations Testing EnvironmentsSystemconfig.h Extending the Example Design Simulation Support Scripts, etcLimitations 10 11 12 13 14 15 16 ... Bytes Document ConventionsAcronyms & Definitions ByteTitle Description Related Documents