Intel IXP1200 manual Related Documents, Title Description

Page 58

IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

Figure 39. Definitions (Continued)

	Term	Definition

	PDU	Protocol Data Unit

	Rosetta	Intel IXB8055 IX Bus to Utopia Bridge

	RTM	Route Table Manager

	Slow Port	A port that does not have dedicated status lines, and
	Slow Port	must poll for status
		must poll for status

	Transactor	IXP1240 Software Simulator

	UBR	Unspecified Bit Rate

	VC	Virtual Circuit

12.0Related Documents

Title	Description

RFC1577	Classical IP over ATM.

	Release notes bundled with source code.
README.txt	There are two README.txt files. One is in the atm_ether project source
README.txt	directory, and is a "Quick Start and Source Code Guide." The second
	README.txt file can be found in the vxworks subdirectory, and describes
	how to run the project on hardware.

IXP1200 Network Processor
RFC 1812 Compliant Layer 3
Forwarding Example Design
Implementation Details

IXP1240 Software Reference
Manual

IXP1240 Development Tools
User’s Guide

RFC 1812 Requirements of IP
Version 4 Routers

58	Application Note

Modified on: 3/20/02,

Image 58

Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Purpose of ATM Example Design IntroductionScope of Example Design Supported / Not Implemented Functions Configuration DescriptionBackground Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box System Programming Model System OverviewHardware StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables ATM to Ethernet Data Flow Data FlowVC Lookup IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowATM Receive Microengine Microengine Functional BlocksMicroengine Initialization StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Receive Structure Ethernet Transmit MicroengineEthernet Receive High Level Algorithm Ethernet Transmit Structure CRC-32 Calculations using IXP1240/1250 HardwareCRC-32 Hardware Checking on Receive Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorCRC-32 Checker and Generator High Level Algorithm Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryBuffer Offset Buffer Index Entry DescriptionCell data11 Entry Description Virtual Circuit Lookup Table Cache VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration VC Cache StructureIP Table Function IP Lookup TableVC Cache API IP Table StructureMtuchange IP Table Management APIRoutetableinit AtmrouteaddRoutedelete EnetrouteaddRtentinfo RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8Next BD Last Quad Queue Index Sram Buffer Descriptor FormatATM Header Entry Description 2 3 4 Dram Data Buffer Format2 3 4 5 6 7 8 Bytes Enet SrcAdrSequencehandle Usage Sequence Numbers sequence.ucSystem Limit on Packet Buffers API Call DescriptionExample Message Queues msgq.ucUsage Model Step Sequence Operation Bakery Line AnalogyMsgqinitregs Msgqhandle ParametersMsgqinitqueue MsgqsendMsgqreceive RamoptionBuffer Descriptor Queues bdq.uc 1.1 FeaturesFeature Description BDQ Management MacrosCounters CountCounter Base Address Global ParametersUse of the Counter Subsystem Counter Index#define Statement Description Global Counter Enable and FlagsCounter Flags Counter Group DescriptionCounterinc Counters.uc CounterresetPortcounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutexvectorenter Mutex VectorsMutexvectorinit MutexvectorexitInter-Thread Signalling Project Configuration / Modifying the Example DesignProjectconfig.h Systemconfig.h Testing EnvironmentsSwitching Between Hardware Configurations Limitations Simulation Support Scripts, etcExtending the Example Design Byte Document ConventionsAcronyms & Definitions 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description