Intel IXP1200 manual Execution Environment, Software

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

A 33-byte IP packet overflows into 2 cells, requiring 53 more bytes on the input wire. This effectively slows down the input rate, and the theoretical best-case Ethernet Transmit bandwidth for this input drops to 475Mbps, well within the capacity of the 8 100Mbps Ethernet ports. Indeed, only in the one-cell/PDU case does the Ethernet transmit bandwidth requirement exceed the 800Mbps available.

As packets grow larger, the net effect of overflowing to the next cell is smaller. However, the peaks in maximum bandwidth are also lower, reflecting the additional ATM header that is needed for each additional cell in the PDU.

The following figure identifies the expected aggregate Ethernet transmit bandwidth for ATM OC-3 and OC-12 wire-rate input:

Figure 3. Expected Ethernet Transmit Bandwidth

1.4Execution Environment

1.4.1Software

The software execution environment supported by the Developer’s Workbench is described in the README.txt file that accompanies the source code files for the project. This includes descriptions of the directory and file structure, and project reconfiguration instructions. See Section 5.0 for additional information on configuring the project.

The software simulation of the example design consumes test data streams from the Data Stream feature of the Developer’s Workbench or through a network simulator Dynamic Linked Library (DLL). Sample Ethernet and ATM data streams are provided.

Application Note

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Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Scope of Example Design IntroductionPurpose of ATM Example Design Ethernet, IP and AAL5 Protocol Processing Configuration DescriptionBackground Supported / Not Implemented FunctionsSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box Hardware System OverviewSystem Programming Model System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables VC Lookup Data FlowATM to Ethernet Data Flow ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationStructure Microengine Functional BlocksMicroengine Initialization ATM Receive MicroengineOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Receive High Level Algorithm Ethernet Transmit MicroengineEthernet Receive Structure CRC-32 Hardware Checking on Receive CRC-32 Calculations using IXP1240/1250 HardwareEthernet Transmit Structure First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCCRC-32 Computation Software Subsystems & Data StructuresVirtual Circuit Lookup Table atmvctable.uc CRC-32 Checker and Generator High Level AlgorithmVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cCell data11 Entry Description Entry DescriptionBuffer Offset Buffer Index VC Cache Structure VC Cache Function 1.1 OC-12 Configuration1.2 OC-3 Configuration Virtual Circuit Lookup Table CacheIP Table Structure IP Lookup TableVC Cache API IP Table FunctionAtmrouteadd IP Table Management APIRoutetableinit MtuchangeRthelp EnetrouteaddRtentinfo Routedelete2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersATM Header Entry Description Sram Buffer Descriptor FormatNext BD Last Quad Queue Index Enet SrcAdr Dram Data Buffer Format2 3 4 5 6 7 8 Bytes 2 3 4API Call Description Sequence Numbers sequence.ucSystem Limit on Packet Buffers Sequencehandle UsageStep Sequence Operation Bakery Line Analogy Message Queues msgq.ucUsage Model ExampleMsgqsend Msgqhandle ParametersMsgqinitqueue MsgqinitregsRamoption MsgqreceiveBDQ Management Macros 1.1 FeaturesFeature Description Buffer Descriptor Queues bdq.ucCount CountersCounter Index Global ParametersUse of the Counter Subsystem Counter Base AddressCounter Group Description Global Counter Enable and FlagsCounter Flags #define Statement DescriptionPortcounterinc Counters.uc CounterresetCounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorexit Mutex VectorsMutexvectorinit MutexvectorenterProjectconfig.h Project Configuration / Modifying the Example DesignInter-Thread Signalling Switching Between Hardware Configurations Testing EnvironmentsSystemconfig.h Extending the Example Design Simulation Support Scripts, etcLimitations 10 11 12 13 14 15 16 ... Bytes Document ConventionsAcronyms & Definitions ByteTitle Description Related Documents