Intel IXP1200 manual System Overview, System Programming Model, Hardware

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

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Figure 5. Developer’s Workbench - IX Bus Device Status Window

1.4.2Hardware

The README.txt file contained in the vxworks subdirectory of the project source code describes how to build and run the project on hardware using VxWorks®. While the project runs in simulation mode by default, some simple changes to the project configuration must be made before it will run on hardware. To run on hardware, Tornado 2.1® as well as the IXP1200 Developer’s Workbench 2.01 need to be installed on the host system. Further details may be found in the README.txt file in the vxworks subdirectory.

2.0System Overview

2.1System Programming Model

Figure 6 shows the system hardware, as seen by the software. Data flows from the receive ports on the left, through the IXP12xx’s RFIFO and its various hardware resources, and then to the TFIFO and out the transmit ports on the right. (While logically independent, receive and transmit ports for each interface are implemented in the same physical hardware package. The figure uses a single block arrow to illustrate 1-4 ATM ports, and 1-8 Ethernet ports, depending on the configuration.)

Application Note

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Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Purpose of ATM Example Design IntroductionScope of Example Design Background Configuration DescriptionSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box System Programming Model System OverviewHardware System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables ATM to Ethernet Data Flow Data FlowVC Lookup ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationMicroengine Initialization Microengine Functional BlocksATM Receive Microengine StructureOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Receive Structure Ethernet Transmit MicroengineEthernet Receive High Level Algorithm Ethernet Transmit Structure CRC-32 Calculations using IXP1240/1250 HardwareCRC-32 Hardware Checking on Receive First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCVirtual Circuit Lookup Table atmvctable.uc Software Subsystems & Data StructuresCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cBuffer Offset Buffer Index Entry DescriptionCell data11 Entry Description 1.2 OC-3 Configuration VC Cache Function 1.1 OC-12 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureVC Cache API IP Lookup TableIP Table Function IP Table StructureRoutetableinit IP Table Management APIMtuchange AtmrouteaddRtentinfo EnetrouteaddRoutedelete Rthelp2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersNext BD Last Quad Queue Index Sram Buffer Descriptor FormatATM Header Entry Description 2 3 4 5 6 7 8 Bytes Dram Data Buffer Format2 3 4 Enet SrcAdrSystem Limit on Packet Buffers Sequence Numbers sequence.ucSequencehandle Usage API Call DescriptionUsage Model Message Queues msgq.ucExample Step Sequence Operation Bakery Line AnalogyMsgqinitqueue Msgqhandle ParametersMsgqinitregs MsgqsendRamoption MsgqreceiveFeature Description 1.1 FeaturesBuffer Descriptor Queues bdq.uc BDQ Management MacrosCount CountersUse of the Counter Subsystem Global ParametersCounter Base Address Counter IndexCounter Flags Global Counter Enable and Flags#define Statement Description Counter Group DescriptionCounterinc Counters.uc CounterresetPortcounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorinit Mutex VectorsMutexvectorenter MutexvectorexitInter-Thread Signalling Project Configuration / Modifying the Example DesignProjectconfig.h Systemconfig.h Testing EnvironmentsSwitching Between Hardware Configurations Limitations Simulation Support Scripts, etcExtending the Example Design Acronyms & Definitions Document ConventionsByte 10 11 12 13 14 15 16 ... BytesTitle Description Related Documents