Intel IXP1200 Document Conventions, Acronyms & Definitions, 10 11 12 13 14 15 16 ... Bytes

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

10.0Document Conventions

In illustrations of 32-bit registers, or data structures in memory; smaller addresses appear toward the top of the figure, - as they would appear in a memory dump on the screen. Bit positions are numbered from the right to the left.

Figure 37. Illustration of Array of 32-bit Words

bits	3	3	2	2	2	2	2	2	2	2	2	2	1	1	1	1	1	1	1	1	1	1	9	8	7	6	5	4	3	2	1	0
bits	1	0	9	8	7	6	5	4	3	2	1	0	9	8	7	6	5	4	3	2	1	0	9	8	7	6	5	4	3	2	1	0
address
address				Byte 0								Byte 1								Byte 2								Byte 3
n				Byte 0								Byte 1								Byte 2								Byte 3
n
address
address				Byte 4								Byte 5								Byte 6								Byte 7
n+1				Byte 4								Byte 5								Byte 6								Byte 7
n+1
address
address				Byte 8								Byte 9								Byte 10								Byte 11
n+2				Byte 8								Byte 9								Byte 10								Byte 11
n+2

Bytes are numbered from left to right as shown in the array in Figure 37, as well as in the example byte sequence inFigure 38. Bytes of a word are numbered starting at the most significant byte.

Figure 38. Illustration of Byte Sequence

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 ... Bytes

Ethernet Dest. Address

Ethernet Source Address

Type

IP... .. IP

11.0Acronyms & Definitions

Figure 39. Definitions

	Term	Definition

	AAL	ATM Adaptation Layer

	AAL5	ATM Adaption Layer 5 (data)

	API	Application Programming Interface

	ARP (or ATM ARP)	Address Resolution Protocol

	ATM	Asynchronous Transfer Mode

	BDQ	Buffer Descriptor Queue

	CRC	Cyclic Redundancy Check

	CS (or AAL5-CS)	Convergence Sub-Layer

	DLL	Dynamic Link Library

	DWBF	Developer’s Workbench - Integrated Development
	DWBF	environment for the IXP1240 Network Processor
		environment for the IXP1240 Network Processor

	Fast Port	A port that has its own dedicated status lines

	GPR

	IP	Internet Protocol

	MAC	Media Access Controller

Application Note

57

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Background Configuration DescriptionSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingSAR Frame and PDU Length vs. IP Packet LengthFrame and PDU Length vs. IP Packet Length Expected Ethernet Transmit BandwidthSoftware Execution EnvironmentDeveloper’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware System Programming Model StrongARM Core SoftwareATM TX Software PartitioningLookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup ATM to Ethernet Processing Steps IP Lookup TableEthernet to ATM Data Flow StrongARM Core InitializationMicroengine Initialization Microengine Functional BlocksATM Receive Microengine StructureOC-12 Port OC-3 Ports High Level AlgorithmATM Transmit High Level Algorithm ATM Transmit MicroengineEthernet Receive Microengine IP-Router MicroengineEthernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive First Cell of a PDU in Rfifo and in Dram Bytes Big Endian DiagramTransmit Alignment CRC-32 Hardware Generation on TransmitFunctional Differences between Checker and Generator CRC-32 Checker and Generator Microengines Soft-CRCVirtual Circuit Lookup Table atmvctable.uc Software Subsystems & Data StructuresCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Primary VC Table Vctablelinear StructureVC Table Entry VC Table Management API atmutils.cEntry Description Buffer Offset Buffer IndexCell data11 Entry Description 1.2 OC-3 Configuration VC Cache Function 1.1 OC-12 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureVC Cache API IP Lookup TableIP Table Function IP Table StructureRoutetableinit IP Table Management APIMtuchange AtmrouteaddRtentinfo EnetrouteaddRoutedelete Rthelp2 3 4 5 6 7 8 Sram Buffer Descriptors and Dram Data BuffersSram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description 2 3 4 5 6 7 8 Bytes Dram Data Buffer Format2 3 4 Enet SrcAdrSystem Limit on Packet Buffers Sequence Numbers sequence.ucSequencehandle Usage API Call DescriptionUsage Model Message Queues msgq.ucExample Step Sequence Operation Bakery Line AnalogyMsgqinitqueue Msgqhandle ParametersMsgqinitregs MsgqsendRamoption MsgqreceiveFeature Description 1.1 FeaturesBuffer Descriptor Queues bdq.uc BDQ Management MacrosCount CountersUse of the Counter Subsystem Global ParametersCounter Base Address Counter IndexCounter Flags Global Counter Enable and Flags#define Statement Description Counter Group DescriptionCounters.uc Counterreset CounterincPortcounterinc Intotaldiscards Portcounterinc AlgorithmCountersprint Counters.c CountersinitAtmtxcrcbadbd Global $transfer Register Name Manager xfer.ucMutexvectorinit Mutex VectorsMutexvectorenter MutexvectorexitProject Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design Acronyms & Definitions Document ConventionsByte 10 11 12 13 14 15 16 ... BytesTitle Description Related Documents