Intel IXP1200 manual Developer’s Workbench ATM Data Stream Dialog Box

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

Figure 4 shows how data stream PDUs can be created in the Workbench for ATM, Ethernet, IP, and other protocol data streams. These data streams can then be assigned to feed different ports. To test how the example design performs IP routing, different destination IP addresses can be chosen in the PDU.

Figure 4. Developer’s Workbench - ATM Data Stream Dialog Box

Figure 5 shows the IX Bus Device Status window. This window gives a continually updated snapshot of IX Bus activity. It can be used to gain an overall picture of what data is being transferred over the IX Bus "on-the-fly", and the data or wire transmission rate. The Data Streaming feature and the IX Bus Device Status window are both documented in the IXP1200 Development Tools User’s Guide.

In the simulation environment, the IP and ATM VC table management software that normally run on the StrongARM core are emulated with a combination of Transactor (simulator) foreign models and interpreted Transactor scripts.

12	Application Note

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Configuration Description BackgroundSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowMicroengine Functional Blocks Microengine InitializationATM Receive Microengine StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorSoftware Subsystems & Data Structures Virtual Circuit Lookup Table atmvctable.ucCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryEntry Description Buffer Offset Buffer IndexCell data11 Entry Description VC Cache Function 1.1 OC-12 Configuration 1.2 OC-3 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureIP Lookup Table VC Cache APIIP Table Function IP Table StructureIP Table Management API RoutetableinitMtuchange AtmrouteaddEnetrouteadd RtentinfoRoutedelete RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8Sram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description Dram Data Buffer Format 2 3 4 5 6 7 8 Bytes2 3 4 Enet SrcAdrSequence Numbers sequence.uc System Limit on Packet BuffersSequencehandle Usage API Call DescriptionMessage Queues msgq.uc Usage ModelExample Step Sequence Operation Bakery Line AnalogyMsgqhandle Parameters MsgqinitqueueMsgqinitregs MsgqsendMsgqreceive Ramoption1.1 Features Feature DescriptionBuffer Descriptor Queues bdq.uc BDQ Management MacrosCounters CountGlobal Parameters Use of the Counter SubsystemCounter Base Address Counter IndexGlobal Counter Enable and Flags Counter Flags#define Statement Description Counter Group DescriptionCounters.uc Counterreset CounterincPortcounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutex Vectors MutexvectorinitMutexvectorenter MutexvectorexitProject Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design Document Conventions Acronyms & DefinitionsByte 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description