Intel IXP1200 manual Ethernet Transmit Microengine, Ethernet Receive Structure

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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design

•For ATM destinations, enqueue to the ATM Transmit microengine, or for software CRC, to the appropriate AAL5 CRC-32 generation queues.

The ETHERNET_LOOPBACK build option enables routing packets from Ethernet Receive ports to Ethernet Transmit ports. This is useful for equipment checkout in the lab. If this option is not defined, packets received from ethernet ports which route to ethernet output ports are discarded with IP_NO_ROUTE exception. If this option is defined, the packets are forwarded as requested.

3.4.1Ethernet Receive Structure

There are four identical threads on each Ethernet receive microengine. Each thread services a specific port and uses a specific RFIFO element.

3.4.2Ethernet Receive High Level Algorithm

Figure 15. Ethernet Receive High Level Algorithm

while(1)

if(no receive buffer in hand) allocate a receive buffer

receive MPKT from MAC to RFIFO if(SOP)

read link layer header from RFIFO if (not Ethernet)

record output queue to be to StrongARM core

else

transfer end of MPKT from RFIFO to DRAM read IP header from RFIFO

if (IP header checksum error) remember to discard this packet

endif

update IP header TTL and checksum ip_lookup()

write LLC/SNAP and modified IP header to DRAM endif

else // !SOP

extract byte count from receive state transfer MPKT from RFIFO to DRAM data buffer

endif if(EOP)

write AAL5 trailer

enqueue PDU to ATM transmitter endif

3.5Ethernet Transmit Microengine

The Ethernet Transmit microengine is rooted in ether_tx_threads.uc, which simply includes system_init.uc, invokes system_init(), sets some definitions, and includes tx_ether100m.uc from the 16-port Ethernet example design on the 2.01 SDK.

Other than that change, there is only one other difference between this Ethernet transmitter and the implementation used by SDK example designs like L3fwd8_1f. With RFC1812 enabled, the SDK example designs place the Ports-With-Packets (PWP) vector in SRAM and polls it to find packets to send. This design uses a more efficient implementation that polls an scratchpad resident PWP vector for the data plane, and checks for a signal before polling an SRAM resident PWP vector to consume packets from the StrongARM core.

24	Application Note

Modified on: 3/20/02,

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Contents IXP1200 Network Processor Family Application Note Contents Virtual Circuit Lookup Table Cache Limitations Figures Introduction Purpose of ATM Example DesignScope of Example Design Configuration Description BackgroundSupported / Not Implemented Functions Ethernet, IP and AAL5 Protocol ProcessingFrame and PDU Length vs. IP Packet Length SARExpected Ethernet Transmit Bandwidth Frame and PDU Length vs. IP Packet LengthExecution Environment SoftwareDeveloper’s Workbench ATM Data Stream Dialog Box System Overview System Programming ModelHardware StrongARM Core Software System Programming ModelSoftware Partitioning ATM TXLookup Tables Data Flow ATM to Ethernet Data FlowVC Lookup IP Lookup Table ATM to Ethernet Processing StepsStrongARM Core Initialization Ethernet to ATM Data FlowMicroengine Functional Blocks Microengine InitializationATM Receive Microengine StructureHigh Level Algorithm OC-12 Port OC-3 PortsATM Transmit Microengine ATM Transmit High Level AlgorithmIP-Router Microengine Ethernet Receive MicroengineEthernet Transmit Microengine Ethernet Receive StructureEthernet Receive High Level Algorithm CRC-32 Calculations using IXP1240/1250 Hardware Ethernet Transmit StructureCRC-32 Hardware Checking on Receive Bytes Big Endian Diagram First Cell of a PDU in Rfifo and in DramCRC-32 Hardware Generation on Transmit Transmit AlignmentCRC-32 Checker and Generator Microengines Soft-CRC Functional Differences between Checker and GeneratorSoftware Subsystems & Data Structures Virtual Circuit Lookup Table atmvctable.ucCRC-32 Checker and Generator High Level Algorithm CRC-32 ComputationVctablehashed Structure Vctablelinear Structure Primary VC TableVC Table Management API atmutils.c VC Table EntryEntry Description Buffer Offset Buffer IndexCell data11 Entry Description VC Cache Function 1.1 OC-12 Configuration 1.2 OC-3 ConfigurationVirtual Circuit Lookup Table Cache VC Cache StructureIP Lookup Table VC Cache APIIP Table Function IP Table StructureIP Table Management API RoutetableinitMtuchange AtmrouteaddEnetrouteadd RtentinfoRoutedelete RthelpSram Buffer Descriptors and Dram Data Buffers 2 3 4 5 6 7 8Sram Buffer Descriptor Format Next BD Last Quad Queue IndexATM Header Entry Description Dram Data Buffer Format 2 3 4 5 6 7 8 Bytes2 3 4 Enet SrcAdrSequence Numbers sequence.uc System Limit on Packet BuffersSequencehandle Usage API Call DescriptionMessage Queues msgq.uc Usage ModelExample Step Sequence Operation Bakery Line AnalogyMsgqhandle Parameters MsgqinitqueueMsgqinitregs MsgqsendMsgqreceive Ramoption1.1 Features Feature DescriptionBuffer Descriptor Queues bdq.uc BDQ Management MacrosCounters CountGlobal Parameters Use of the Counter SubsystemCounter Base Address Counter IndexGlobal Counter Enable and Flags Counter Flags#define Statement Description Counter Group DescriptionCounters.uc Counterreset CounterincPortcounterinc Portcounterinc Algorithm IntotaldiscardsCounters.c Countersinit CountersprintGlobal $transfer Register Name Manager xfer.uc AtmtxcrcbadbdMutex Vectors MutexvectorinitMutexvectorenter MutexvectorexitProject Configuration / Modifying the Example Design Inter-Thread SignallingProjectconfig.h Testing Environments Systemconfig.hSwitching Between Hardware Configurations Simulation Support Scripts, etc LimitationsExtending the Example Design Document Conventions Acronyms & DefinitionsByte 10 11 12 13 14 15 16 ... BytesRelated Documents Title Description